Semiconductor integrated circuit and method of production of same

ABSTRACT

A semiconductor integrated circuit, able to repair a fault and normally operate as an overall circuit even when a fault occurs in a portion of the circuit, and able to reduce a change of signal delay along with the repair of the fault, including N (larger than 2) number of circuit modules which can replace each other&#39;s functions; circuit blocks each including R (larger than 1 but smaller than N) number of I/O units for outputting at least one signal to one circuit module, and receiving at least one signal generated in the one circuit module; and a circuit module selection unit configured to select R number of circuit modules from among the N number of circuit modules in response to a control signal, connect the selected R number of circuit modules and R number of I/O units of the circuit block in a 1:1 correspondence, and connect one circuit module selected from at least two circuit modules in response to the control signal to each of the R number of I/O units, and a method of producing the same.

CROSS REFERENCE TO RELATED APPLICATION

The present invention contains subject matter related to Japanese PatentApplication No. 2005-202818 filed in the Japan Patent Office on Jul. 12,2006, the entire contents of which being incorporated herein byreference.

BACKGROUND OF THE INVENTION

1. Field of Invention

The present invention relates to a semiconductor integrated circuithaving a plurality of circuit modules which can replace each other'sfunctions and a method of production of the same, more particularlyrelates to a semiconductor integrated circuit reducing the drop in yielddue to faults of circuit modules.

2. Description of the Related Art

In recent semiconductor integrated circuits, the processing dimensionsare becoming increasingly finer the circuit configurations are becomingincreasingly larger in scale. The drop in yield due to faults inproduction has become serious. Therefore, the technique of previouslyproviding redundant circuits at parts of the overall circuit andreplacing faulty portions by these redundant circuits to thereby preventthe entire semiconductor chip from being discarded as a defectiveproduct has been proposed.

In the method of generation of logical circuit data of a fieldprogrammable gate array (FPGA) disclosed in, for example, JapanesePatent No. 3491579, the need for avoiding faults is judged from faultinformation and logic information and, if necessary, the logicinformation is changed so that the function of any faulty portion isreplaced by an empty portion.

In the above FPGA, where a basic unit of configuration of the logiccircuit, that is, a basic cell, fails, the interconnect route is changedso as to bypass it. Detour interconnects for avoiding faults differ inaccordance with the state of occurrence of the faults. It is difficultto predict in advance how the interconnect route will changed. For thisreason, it is difficult to set a clear delay margin that can satisfy thedesired delay conditions no matter which of the basic cells fails, so itis necessary to set a considerably large margin considering thepossibility that the delay characteristic will remarkably degrade.

Further, in the semiconductor device disclosed in Japanese Patent No.3192220, data is transferred among a plurality of circuit modules bymemory map type addressing. ID codes are assigned to circuit modules. Bychanging the ID codes to control the destination of data, a faultycircuit module can be replaced by a redundant circuit module.

In this semiconductor device, how long the data transfer distancebetween circuit modules becomes may greatly vary in accordance with thestate of occurrence of the faults, therefore it is necessary toprescribe the operation of each circuit module by envisioning the casewhere all circuit modules are separated from each other to the maximumlimit. Accordingly, it is necessary to set a considerably large delaymargin at the time of design and it is hard to optimize the performanceof the entire system.

SUMMARY OF THE INVENTION

It is therefore desirable in present invention to provide asemiconductor integrated circuit able to make the overall circuitnormally operate by repairing any fault occurring in a part of thecircuit and, at the same time, able to reduce the change of the signaldelay accompanying the repair of faults and a method of production ofthe same.

According to a first embodiment of the in invention, there is provided asemiconductor integrated circuit having N (N indicates an integer ofN≧2) number of circuit modules which can replace each other's functions;circuit blocks each having R (R indicates an integer of 1≦R<N) number ofinput/output units for outputting at least one signal to one circuitmodule and receiving as input at least one signal generated in that onecircuit module; and a circuit module selection unit configured to selectR number of circuit modules from among the N number of circuit modulesin response to a control signal, connecting the selected R number ofcircuit modules and R number of input/output units of the circuit blockin a one-to-one correspondence, and connect one circuit module selectedin response to the control signal from at least two circuit modules toeach of the R number of input/output units.

Preferably, the circuit includes a control unit comprised for generatingthe control signal of the circuit module selection unit so that a faultycircuit module among the N number of circuit modules is disconnectedfrom the R number of input/output units.

According to the above configuration, it becomes possible to arrange twoor more circuit modules connected to the same input/output unit so thata difference of distances from this input/output unit becomes small.When the difference of distances between the input/output unit and thecircuit modules becomes small, the difference of lengths ofinterconnects connecting the two becomes small, therefore the change ofthe signal delay occurring when the connection between a circuit moduleand the input/output unit is switched along with repair etc. of a faultbecomes small.

The semiconductor integrated circuit may include a storage unit forstoring a signal designating (N−R) number of circuit modules whichshould be disconnected from the R number of input/output units. In thiscase, the control unit may generate the control signal in accordancewith the signal stored in the storage unit.

Further, the semiconductor integrated circuit may include a signal inputunit for receiving as input a signal designating (N−R) number of circuitmodules which should be disconnected from the R number of input/outputunits. In this case, the control unit may generate the control signal inaccordance with the signal input to the signal input unit.

When both of the storage unit and the signal input unit are provided,the control unit may generate the control signal in accordance with thesignal input to the signal input unit where a signal having apredetermined initial value is stored in the storage unit and generatethe control signal in accordance with the signal stored in the storageunit where a signal having a value different from the initial value isstored in the storage unit.

The R number of input/output units may include R number of input/outputunits from a first input/output unit to an R-th input/output unit. The Nnumber of circuit modules may include (R+1) circuit modules from a firstcircuit module to an (R+1)th circuit module. The circuit moduleselection unit may select one of an i-th circuit module (i indicates aninteger of 1≦i≦R) or an (i+1)th circuit module in response to thecontrol signal and connect the selected circuit module to the i-thinput/output unit. In this case, the R number of input/output units maybe arranged in numerical order at equal intervals, and the i-th circuitmodule and the (i+1)th circuit module may be arranged at positions sothat the distances from the i-th input/output unit become equal.

Combinations of at least two circuit modules which can be connected toeach of the R number of input/output units via (through-hole) thecircuit module selection unit may be determined so that a maximum valueof delays of all signal paths connecting the R number of input/outputunits and the N number of circuit modules via (through-hole) the circuitmodule selection unit becomes the smallest. Alternatively, it may bedetermined so that a sum of delays of all signal paths connecting the Rnumber of input/output units and the N number of circuit modules via(through-hole) the circuit module selection unit becomes the smallest.Alternatively, it may be determined so that a sum of delays of all ofthe signal paths becomes the smallest within a range where the maximumvalue of delays of all signal paths connecting the R number ofinput/output units and the N number of circuit modules via(through-hole) the circuit module selection unit does not exceed apredetermined upper limit value.

Preferably, in the circuit block and the circuit module selection unit,the interval of interconnects belonging to the same interconnect layeris wider in comparison with the N number of circuit modules. Further,preferably, in the circuit block and the circuit module selection unit,the number of vias (through-hole) used for connecting interconnectsbelonging to different interconnect layers is larger in comparison withthe N number of circuit modules. Due to this, the probability ofoccurrence of faults of the circuit block and the circuit moduleselection unit is reduced, and the yield is improved.

The N number of circuit modules may have a higher density of circuitelements per unit area in comparison with the circuit block and thecircuit module selection unit. Due to this, the area of the circuitbecomes smaller.

The semiconductor integrated circuit may have N number of power supplyswitch circuits each of which is inserted in a power supply line of eachof the N number of circuit modules and shutting off the supply of thepower to (N−R) number of circuit modules not connected to the R numberof input/output units in a one-to-one correspondence in response to thecontrol signal. Due to this, wasteful consumption of power in unusedcircuit modules is reduced. Further, by disconnecting a faulty circuitmodule from the power supply system, the yield is improved.

According to a second embodiment of the present invention, there isprovided a semiconductor integrated circuit including a plurality ofcircuit module blocks each including at least three circuit modules;circuit blocks each having a plurality of input/output units configuredto output at least one signal to one circuit module and receiving asinput at least one signal generated in the one circuit module; and acircuit module selection unit configured to select R (R indicates aninteger of 1≦R<N) number of circuit modules from among N (N indicates aninteger of N≧2) number of circuit modules included in each circuitmodule block in response to the input control signal, connect theselected R number of circuit modules and R number of input/output unitsof the circuit block in a one-to-one correspondence, and connect onecircuit module selected from at least two circuit modules in response tothe control signal to each of a plurality of input/output units of thecircuit block. Circuit modules included in the same circuit module blockcan replace each other's functions. Preferably, the circuit has acontrol unit configured to generate the control signal of the circuitmodule selection unit so that any faulty circuit module among the Nnumber of circuit modules included in the circuit module block isdisconnected from the R number of input/output units.

According to the above configuration, it becomes possible to arrange twoor more circuit modules connected to the same input/output unit so thatthe difference of distances from the input/output unit becomes small.Further, it becomes possible to repair the faults of a plurality oftypes of circuit modules.

The entire set of circuit modules included in the plurality of circuitmodule blocks may include a plurality of partial sets each of which isconfigured by a plurality of circuit modules and has no dealings withthe others. In this case, when a circuit module belonging to a partialset is disconnected from an input/output unit, the control unit maygenerate the control signal so as to disconnect all other circuitmodules belonging to the same partial set as the disconnected circuitmodule from the input/output unit. Due to this, the circuitconfiguration becomes simpler in comparison with the case where thecontrol signal is generated in the control unit so as to disconnectindividual circuit modules from the input/output units.

The semiconductor integrated circuit may have a plurality of powersupply switch circuits each of which is inserted in the power supplyline of each of the plurality of partial sets and shut off the supply ofthe power to the partial set disconnected from the input/output units.Due to this, wasted consumption of power in the unused circuit modulesis reduced. Further, by disconnecting a faulty circuit module from thepower supply system, the yield is improved. The circuit configurationbecomes simpler in comparison with the case where the power supplyswitch circuits are inserted into the power supply lines of individualcircuit modules.

The semiconductor integrated circuit may have a circuit module commonlyused by a plurality of circuit module blocks. This circuit module ispreferably provided with a function of encompassing all or part of thefunctions of the other circuit modules included in the plurality ofcircuit module blocks. Due to this, it becomes possible to replace theredundant circuit provided for each circuit module block by the commonlyused circuit module.

According to a third embodiment of the present invention, there isprovided a method of producing a semiconductor integrated circuitcomprising a first step, a second step, a third step, and a fourth step.

The first step comprises forming, on a semiconductor substrate, acircuit having N (N indicates an integer of N≧2) number of circuitmodules which can replace each other's functions, circuit blocks eachhaving R (R indicates an integer of 1≦R<N) input/output units foroutputting at least one signal to one circuit module and receiving asinput at least one signal generated in the one circuit module, a circuitmodule selection unit configured to select R number of circuit modulesfrom among the N number of circuit modules in response to the inputcontrol signal and connect the selected R number of circuit modules andR number of input/output units of the circuit block in a one-to-onecorrespondence, a storage unit for storing a signal having apredetermined initial value, a signal input unit for receiving as inputa signal designating (N−R) number of circuit modules which should bedisconnected from the R number of input/output units, and a control unitconfigured to generate the control signal in accordance with a signalinput to the signal input unit when the signal having the initial valueis stored in the storage unit and generate the control signal inaccordance with the signal stored in the storage unit when a signalhaving a value different from the initial value is stored in the storageunit.

The second step comprises inputting a signal designating (N−R) number ofcircuit modules to the signal input unit and inspecting the R number ofcircuit modules connected to the R number of input/output units inaccordance with the input signal.

The third step comprises inputting a signal designating a new (N−R)number of circuit modules including a faulty circuit module to thesignal input unit and again performs the inspection of the second stepwhen a faulty circuit module is detected in the inspection of the secondstep.

The fourth step comprises determining a signal designating the (N−R)number of circuit modules which should be disconnected from the R numberof input/output units and writing it into the storage unit in accordancewith a signal input to the signal input unit when a faulty circuitmodule is not detected in the inspection of the second step.

According to the present invention, a plurality of circuit modulesconnected to the same input/output unit can be arranged so that thedifference of distances from the input/output unit becomes small,therefore the change of the signal delay occurring when connectionbetween the input/output unit and a circuit module is switched alongwith fault repair can be made smaller.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects and features of the present invention willbecome clearer from the following description of the preferredembodiments given with reference to the attached drawings, wherein:

FIGS. 1A and 1B are diagrams showing an example of the configuration ofa semiconductor integrated circuit according to a first embodiment ofthe present invention;

FIGS. 2A and 2B are diagrams showing an example of a case where a switchcircuit is regarded as belonging to an input/output unit in thesemiconductor integrated circuit shown in FIGS. 1A and 1B;

FIGS. 3A to 3B are diagrams showing an example of the configuration of asemiconductor integrated circuit according to a third embodiment of thepresent invention;

FIGS. 4A to 4C are diagrams showing an example of the configuration of asemiconductor integrated circuit according to a fourth embodiment of thepresent invention;

FIG. 5 is a diagram showing an example of layout of input/output unitsand circuit modules in the semiconductor integrated circuit shown inFIGS. 1A and 1B;

FIGS. 6A and 6B are diagrams showing an example of the layout andinterconnects of input/output units and circuit modules in asemiconductor integrated circuit according to a fifth embodiment of thepresent invention;

FIGS. 7A to 7D are diagrams for explaining the routine of repair in acase where a fault occurs in a circuit module M3 in the semiconductorintegrated circuit shown in FIGS. 6A and 6B;

FIGS. 8A and 8B are diagrams showing an example of the overall circuitlayout of a semiconductor integrated circuit according to the fifthembodiment of the present invention;

FIGS. 9A to 9C are diagrams showing an example where one circuit moduleis commonly used by two circuit module blocks in a semiconductorintegrated circuit according to a sixth embodiment of the presentinvention;

FIGS. 10A and 10B are diagrams showing an example of the overall circuitlayout of a semiconductor integrated circuit according to the sixthembodiment of the present invention;

FIG. 11 is a diagram showing an example of the configuration of asemiconductor integrated circuit according to a seventh embodiment ofthe present invention;

FIG. 12 is a diagram showing an example of fault repair in thesemiconductor integrated circuit shown in FIG. 11;

FIGS. 13A to 13C are diagrams showing a first example of theconfiguration of a semiconductor integrated circuit according to aneighth embodiment of the present invention;

FIGS. 14A to 14C are diagrams showing a second example of theconfiguration of the semiconductor integrated circuit according to theeighth embodiment of the present invention;

FIG. 15 is a first flow chart showing an example of a routine forsearching for a connection pattern for repairing a fault;

FIG. 16 is a second flow chart showing an example of a routine forsearching for a connection pattern for repairing a fault;

FIG. 17 is a third flow chart showing an example of a routine forsearching for a connection pattern for repairing a fault;

FIGS. 18A to 18C are diagrams for explaining a specific example of theconnection pattern search processing;

FIG. 19 is a diagram showing an example of the configuration of asemiconductor integrated circuit according to a ninth embodiment of thepresent invention;

FIG. 20 is a diagram showing an example of the configuration of acircuit module.

FIG. 21 is a diagram showing an example of the configuration of aportion relating to switching control of circuit modules in thesemiconductor integrated circuit shown in FIGS. 18A to 18C;

FIG. 22 is a diagram showing a first example of the configuration of aswitch element for turning on/off a signal transmitted from aninput/output unit to a circuit module;

FIG. 23 is a diagram showing a first example of the configuration of aswitch element for turning on/off a signal transmitted from a circuitmodule to an input/output unit;

FIG. 24 is a diagram showing a second example of the configuration of aswitch element for turning on/off a signal transmitted from aninput/output unit to a circuit module;

FIG. 25 is a diagram showing a second example of the configuration of aswitch element for turning on/off a signal transmitted from a circuitmodule to an input/output unit;

FIG. 26 is a diagram showing a third example of the configuration of aswitch element for turning on/off a signal transmitted from aninput/output unit to a circuit module;

FIG. 27 is a diagram showing a third example of the configuration of aswitch element for turning on/off a signal transmitted from a circuitmodule to an input/output unit;

FIGS. 28A and 28B are plan views showing an example of the structure ofa switch element of a first example of the configuration shown in FIG.22 and FIG. 23;

FIGS. 29A and 29B are plan views showing an example of the structure ofa switch element of a second example of the configuration shown in FIG.24 and FIG. 25;

FIG. 30 is a diagram showing a default connection state of thesemiconductor integrated circuit shown in FIG. 19;

FIG. 31 is a first diagram showing the connection state in a case wherefault repair is carried out in the semiconductor integrated circuitshown in FIG. 19;

FIG. 32 is a second diagram showing the connection state in a case wherefault repair is carried out in the semiconductor integrated circuitshown in FIG. 19;

FIG. 33 is a diagram showing an example of the configuration of asemiconductor integrated circuit according to a 10th embodiment of thepresent invention;

FIG. 34 is a diagram showing an example of the configuration of asemiconductor integrated circuit according to an 11th embodiment of thepresent invention;

FIGS. 35A and 35B are diagrams showing an example of the configurationof a power supply switch circuit;

FIG. 36 is a diagram showing an example of the configuration of asemiconductor integrated circuit according to a 12th embodiment of thepresent invention;

FIG. 37 is a diagram showing the default connection state of thesemiconductor integrated circuit shown in FIG. 36;

FIG. 38 is a first diagram showing the connection state in a case wherefault repair is carried out in the semiconductor integrated circuitshown in FIG. 36;

FIG. 39 is a diagram showing an example of the configuration of asemiconductor integrated circuit according to a 13th embodiment of thepresent invention;

FIG. 40 is a diagram showing an example of the configuration of aprincipal portion of the semiconductor integrated circuit shown in FIG.39;

FIG. 41 is a diagram showing the default connection state of thesemiconductor integrated circuit shown in FIG. 39;

FIG. 42 is a diagram showing the connection state where fault repair iscarried out in the semiconductor integrated circuit shown in FIG. 39;

FIG. 43 is a flow chart showing an example of a method of production ofthe semiconductor integrated circuit shown in FIG. 21; and

FIG. 44 is a diagram showing an example of the configuration of acircuit module selection unit provided with a switch circuit forconnecting a signal input terminal to an interconnect having apredetermined potential.

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment

FIG. 1 is a diagram showing an example of the configuration of asemiconductor integrated circuit according to a first embodiment of thepresent invention. The semiconductor integrated circuit according to thefirst embodiment, for example as shown in FIG. 1A, has circuit modulesM1 to M6, a general circuit block 100, switch circuits SWA1 to SWA5, andswitch circuits SWB1 to SWB5.

Each of the circuit modules M1 to M6 is an embodiment of a circuitmodule of the claims. The general circuit block 100 is an embodiment ofthe circuit block of the claims. The circuit including the switchcircuits SWA1 to SWA5 and SWB1 to SWB5 is an embodiment of the circuitmodule selection unit of the claims. The switch circuits SWA1 to SWA5are an embodiment of a first switch group of the claims. The switchcircuits SWB1 to SWB5 are an embodiment of a second switch group of thepresent invention.

Each of the circuit modules M1 to M6 is a group of circuits having apredetermined function. They can replace each other's functions. All ofthe circuit modules M1 to M6 may have the same circuit configuration orsome circuit modules may have partially different circuit configurationsif they can replace each other's functions.

The circuit modules M1 to M6 may have any circuit configurations andfunctions. For example, they may be digital signal processors (DSP) orother circuits having operation/processing functions or may be circuitsperforming relatively simple logic operations such as LookUp Tables.Alternatively, the plurality of circuits having equivalent functionsincluded in the semiconductor integrated circuit may be handled as onecircuit module. Further, the circuit modules M1 to M6 are not limited todigital circuits, but may be analog circuits.

The general circuit block 100 has input/output units P1 to P5 forexchanging signals with the above circuit modules M1 to M6 and executespredetermined processing in cooperation with these circuit modules. Thegeneral circuit block 100 may have any circuit configuration andfunction and may be for example only interconnects.

Each of the input/output units P1 to P5 outputs at least one signal toone circuit module among the above circuit modules M1 to M6 and, at thesame time, receives as input at least one signal generated in onecircuit module.

All of the input/output units P1 to P5 may input/output the samecombinations of signals or some input/output units may be differenttypes inputting/outputting different combinations of signals. Forexample, when the circuit modules M1 to M6 have three output terminals,an input/output unit for receiving as input signals from all of thesethree output terminals, an input/output unit for receiving as input thesignal from only one output terminal, and so on may be mixed.

A switch circuit SWAi (i indicates an integer from 1 to 5, same truebelow in the present embodiment) is connected between an input/outputunit Pi and a circuit module Mi and turns on or off in response to theinput control signal (not shown). A switch circuit SWBi is connectedbetween the input/output unit Pi and a circuit module M(i+1) and turnson or off in response to the input control signal.

The switch circuits SWA1 to SWA5 and SWB1 to SWB5 configure a circuitmodule selection unit. The circuit module selection unit (SWA1 to SWA5and SWB1 to SWB5) is a circuit for selecting five circuit modules fromamong six circuit modules (M1 to M6) in response to a control signal andconnecting the selected five circuit modules and five input/output units(P1 to P5) in a one-to-one correspondence.

The circuit module selection unit (SWA1 to SWA5 and SWB1 to SWB5)connects one circuit module selected from two circuit modules inresponse to a control signal to each of the five input/output units (P1to P5). Namely, this selects one of the circuit module Mi or the circuitmodule M(i+1) in response to the input control signal and connects theselected circuit module to the input/output unit Pi.

The circuit module selection unit (SWA1 to SWA5 and SWB1 to SWB5)selects five circuit modules so that a faulty circuit module (when thereis no fault, the circuit module previously provided for redundancy)among the six circuit modules is disconnected from all input/outputunits in response to a control signal supplied from for example a notshown control unit.

For example, in the case where a control signal designating thedisconnection of a circuit module Mn (n indicates an integer from 1 to6, same true below in the present embodiment) from all input/outputunits is input, when n is an integer from 2 to 5 (that is, a case wherethe circuit modules M2 to M5 are to be disconnected), the switchcircuits SWA1 to SWA(n−1) are turned on and the switch circuits SWAn toSWA5 are turned off and, at the same time, the switch circuits SWB1 toSWB(n−1) are turned off and the switch circuits SWBn to SWB5 are turnedon. When n is the integer 1 (that is, when the circuit module M1 is tobe disconnected), all of the switch circuits SWA1 to SWA5 turn off, andall of the switch circuits SWB1 to SWB5 turn on. When n is the integer 6(that is, when the circuit module M6 is to be disconnected), all of theswitch circuits SWA1 to SWA5 turn on, and all of the switch circuitsSWB1 to SWB5 turn off.

FIG. 1B shows a connection state of a case where a fault occurs in thecircuit module M3. In this case, a not shown control unit generates acontrol signal so as to disconnect the circuit module M3 from allinput/output units. In response to this control signal, the switchcircuits SWA1 and SWA2 turn on, the switch circuits SWA3, SWA4, and SWA5turn off, the switch circuits SWB1 and SWB2 turn off, and the switchcircuits SWB3, SWB4, and SWB5 turn on. Due to this, the input/outputunit P1 and module M1, the input/output unit P2 and module M2, theinput/output unit P3 and module M4, the input/output unit P4 and moduleM5, the input/output unit P5 and module M6 are connected, and the moduleM3 is disconnected from the general circuit block 100.

According to the semiconductor integrated circuit shown in FIGS. 1A and1B, five circuit modules selected from among six circuit modules (M1 toM6), and five input/output units (P1 to P5) provided in the generalcircuit block 100 are connected in a one-to-one correspondence. Further,one circuit module selected from two circuit modules is connected toeach of the five input/output units (P1 to P5). Due to this, it becomespossible to arrange two circuit modules (Mi, M(i+1)) connected to thesame input/output unit Pi so that the difference of distances from theinput/output unit Pi becomes small. For example, as shown in FIGS. 1Aand 1B, by arranging five input/output units (P1 to P5) in numericalorder (that is in the order of P1, . . . , P5) at equal intervals, twocircuit modules (Mi, M(i+1)) can be arranged so that the distances fromthe input/output unit Pi become equal to each other. By reducing thedifference of distances between the input/output unit and circuitmodules, the difference of lengths of interconnects connecting the twocan be made small. Accordingly, the change of the signal delay occurringwhen switching the connection between a circuit module and aninput/output unit along with fault repair can be made small.

To what degree a change of the signal delay due to fault repair becomecan be correctly predicted based on the positional relationships betweenthe circuit modules Mi and M(i+1) and the input/output unit Pi,therefore, in comparison with a case where correct prediction isdifficult as in for example the previously explained Japanese Patent No.3491579, it becomes possible to estimate the delay margin as small andrealize a circuit operating at a higher speed.

According to the semiconductor integrated circuit shown in FIG. 1, faultrepair can be carried out according to a simple circuit configuration ofselecting one of two circuit modules and connecting it to oneinput/output unit, therefore an increase of circuits and excess powerconsumption can be kept to the lowest limit. For the switch circuit andcontrol unit used for switching the connection and the storage unit forholding fault information, use can be made of circuits which can bedesigned and produced according to a conventional general method,therefore an increase of cost due to the provision of the fault repairfunction can be kept very small.

It is not necessary to add any circuit for fault repair to the generalcircuit block 100, therefore it becomes possible to use conventionalcircuits as they are the design load due to the provision of the faultrepair function can be lightened.

Note that in the semiconductor integrated circuit shown in FIG. 1, fiveinput/output units (P1 to P5) are arranged on a straight line, but thesemay also be arranged on for example a curve or a meandering line orarranged in a zigzag manner. On any line, so far as the input/outputunits P1 to P5 are arranged in numerical order at equal intervals, it ispossible to arrange two circuit modules (Mi, M(i+1)) so that thedistances from the input/output unit Pi become equal to each other.

Second Embodiment

Next, a second embodiment of the present invention will be explained.

In the semiconductor integrated circuit according to the firstembodiment, the portion designed for fault repair (circuit modules M1 toM6) and the portion not designed for fault repair (general circuit block100) were separated. When a fault occurred in the portion not designedfor fault repair, the entire circuit had to be discarded, therefore, inthis portion, desirably the fault rate is lowered as much as possible.Therefore, in the semiconductor integrated circuit according to thesecond embodiment, the “design for manufacturing” (DFM) or othertechnique is used to ensure that the portion not designed for faultrepair (general circuit block 100) becomes more resistant to faults incomparison with the portion designed for fault repair (circuit modulesM1 to M6).

For example, in the general circuit block 100, the interconnect patternsare formed so that the interval between interconnects belonging to thesame interconnect layer becomes greater in comparison with the circuitmodules M1 to M6. Due to this, the probability of occurrence of a faultdue to the short-circuiting of interconnects can be reduced.

In the general circuit block 100, the number of vias (through-hole) usedfor connecting the interconnects belonging to the different interconnectlayers may be increased in comparison with the circuit modules M1 to M6.For example, interconnects usually connected by one via (through-hole)are connected by two vias (through-hole). Due to this, the probabilityof occurrence of faults due to insufficient vias (through-hole) can bereduced.

Conversely, in the circuit modules M1 to M6, the density of circuitelements per unit area may be raised in comparison with the generalcircuit block 100. When the density of the circuit elements becomeshigh, the probability of occurrence of faults becomes high, but in thecircuit modules M1 to M6, effects of fault repair can be expected,therefore, if within a suitable range, there is not that great influenceupon the yield even when faults occur slightly easier. Accordingly, byraising the density of circuit elements in the circuit modules M1 to M6,a reduction of area and an increase in performance of the overallcircuit can be achieved without a great influence upon the yield.

The switch circuits (SWA1 to SWA5 and SWB1 to SWB5) configuring thecircuit module selection unit may be included in the portion designedfor fault repair or may be included in the portion not designed forfault repair. When the switch circuits (SWA1 to SWA5, SWB1 to SWB5) areincluded in the portion not designed for fault repair, the samecountermeasure as that for the general circuit block 100 is applied tothese switch circuits. Namely, a countermeasure for forming theinterconnect patterns so that the interval between interconnectsbelonging to the same interconnect layer becomes broader in comparisonwith the circuit modules M1 to M6, a countermeasure for connectinginterconnects by using a larger number of vias (through-hole) incomparison with circuit modules M1 to M6, etc. are applied. Due to this,the reduction of the yield due to a fault of the switch circuit can besuppressed.

On the other hand, when the switch circuits (SWA1 to SWA5 and SWB1 toSWB5) are included in the portion not designed for fault repair, theprobability of occurrence of a fault becomes higher in comparison withthe case where the above countermeasure is carried out. As the casewhere a fault of the switch circuit exerts an influence upon the overallcircuit, for example, there can be explained a case where the switchcircuit provided in the path for receiving as input a signal to thegeneral circuit block 100 fails due to a short-circuit and a signalhaving a constant voltage is continuously input to the general circuitblock 100 from this failed switch circuit. If the a fault does not occurfrequently, the pitch between interconnects and number of vias(through-hole) can be reduced by including the switch circuits (SWA1 toSWA5, SWB1 to SWB5) in the portion not designed for fault repair,therefore the merit that the area of the circuit can be reduced isobtained.

When the switch circuits (SWA1 to SWA5 and SWB1 to SWB5) are included inthe portion designed for fault repair, for example, as shown in FIG. 1,it can also be regarded that the switch circuits belong to theindividual circuit modules. Namely, it can also be regarded that aswitch circuit SWAj and a switch circuit SWB(j−1) belong to a circuitmodule Mj (j indicates an integer from 2 to 5, same true below in thepresent embodiment), a switch circuit SWA1 belongs to the circuit moduleM1, and a switch circuit SWB5 belongs to the circuit module M6. In thiscase, the layout and interconnects may be designed by regarding thecircuit modules M1 to M6 to which the switch circuits belong as one unitof configuration.

When the switch circuits (SWA1 to SWA5 and SWB1 to SWB5) are included inthe portion not designed for fault repair, for example, as shown inFIGS. 2A and 2B, it may be regarded that the switch circuits belong toindividual input/output units. Namely, it may be regarded that a switchcircuit SWAi and a switch circuit SWBi belong to an input/output unit Pi(i indicates an integer from 1 to 5, same true below in the presentembodiment). In this case, the layout and interconnects may be designedby regarding the input/output units to which the switch circuits belongas one unit of configuration.

Third Embodiment

Next, a third embodiment of the present invention will be explained.

In the semiconductor integrated circuit according to the firstembodiment, the circuit modules M1 to M6 can replace each other'sfunctions, but it is not necessary that all of these circuit moduleshave the same functions. Even in a case where part of the plurality ofcircuit modules have upward compatibility with respect to another part,replacement of functions among circuit modules is possible.

For example, assume that there are circuit modules having a firstfunction and circuit modules having a second function encompassing thisfirst function. In this case, the circuit modules having the secondfunction can replace all functions of the circuit modules having thefirst function. On the other hand, the circuit modules having the firstfunction cannot replace all functions of the circuit modules having thesecond function, but can replace part of the functions. In this way, inthe present specification, when it is described that “the circuitmodules can replace each other's functions”, it includes not only a casewhere circuit modules can replace all functions of other circuitmodules, but also a case where the circuit modules can replace part ofthe functions of other circuit modules.

FIGS. 3A to 3C are diagrams showing an example of the configuration ofthe semiconductor integrated circuit according to the third embodiment.The semiconductor integrated circuit shown in FIGS. 3A to 3C is obtainedby replacing the circuit modules M5 and M6 in the semiconductorintegrated circuit shown in FIGS. 1A and 1B by circuit modules MA5 andMA6 having the upward compatibility with respect to the circuit modulesM1 to M4.

The circuit modules MA5 and MA6 have upward compatibility with respectto the circuit modules M1 to M4, therefore if a there a fault arises inthe latter circuit module, the fault can be repaired by replacing thisby the former circuit module.

When all circuit modules normally operate (FIG. 3A), the circuit moduleM4 is connected to the input/output unit P4, and the circuit module MA5is connected to the input/output unit P5. When there is a fault in thecircuit module M3 (FIG. 3B), the circuit module MA5 is connected to theinput/output unit P4, and the circuit module MA6 is connected to theinput/output unit P5. The circuit module MA5 has upward compatibilitywith respect to the circuit module M4, therefore the circuit module MA5connected to the input/output unit P4 can provide a function equivalentto that of the circuit module M4 to the general circuit block 100. Whenthere is a fault in the circuit module MA5 (FIG. 3C), the circuit moduleMA6 having a function equivalent to that of the circuit module MA5 isconnected to the input/output unit P5.

In this way, in the semiconductor integrated circuit shown in FIGS. 3Ato 3C, the partial high function circuit modules (MA5, MA6) have upwardcompatibility with respect to the other partial low function circuitmodules (M1 to M4). The number of high function circuit modules islarger than the number of input/output units connected to them,therefore a portion of the high function circuit modules becomesredundant. The faults of two types of circuit modules (high function,low function) can therefore be repaired by utilizing redundant highfunction circuit modules. Due to this, it becomes unnecessary tospecially provide redundant low function circuit modules in order torepair low function circuit modules, therefore the increase of thecircuit area can be suppressed.

Fourth Embodiment

Next, a fourth embodiment of the present invention will be explained.

FIG. 4A is a diagram showing all connection paths between fiveinput/output units (P1 to P5) and six circuit modules (M1 to M6). Acombination of connection paths satisfying the condition that one of twocircuit modules is selectively connected with respect to oneinput/output unit and any five circuit modules selected from among sixcircuit modules (M1 to M6) and five input/output units (P1 to P5) areconnected in a one-to-one correspondence among all connection paths asshown in FIG. 4A will be called a “connection set” in the presentembodiment. A connection set can be unambiguously designated by thecombination of two circuit modules which can be connected to each of sixinput/output units. There are a plurality of these connection sets. FIG.4B and FIG. 4C illustrate two among these.

The semiconductor integrated circuit shown in FIG. 4B has the sameconnection set as that of the semiconductor integrated circuit shown inFIGS. 1A and 1B. Namely, one of the circuit modules Mi and M(i+1) isselectively connected with respect to the input/output unit Pi (iindicates an integer from 1 to 5, same true below in the presentembodiment).

On the other hand, in the semiconductor integrated circuit shown in FIG.4C, the circuit module M4 or M6 is connected to the input/output unitP5, the circuit module M4 or M1 is connected to the input/output unitPi, the circuit module M1 or M2 is connected to the input/output unitP2, the circuit module M2 or M3 is connected to the input/output unitP3, and the circuit module M3 or M5 is connected to the input/outputunit P4.

The semiconductor integrated circuit according to the fourth embodimentemploys a connection set selected among a plurality of connection setsexisting in this way so that the change of the electric characteristicsalong with connection switching becomes as small as possible.

The connection set should be determined so that the maximum value ofdelays of all signal paths connecting five input/output units (P1 to P5)and six circuit modules (M1 to M6) via (through-hole) the circuit moduleselection unit (SWA1 to SWA5 and SWB1 to SWB5) becomes the smallest.

The connection set should be determined so that the sum of delays ofthese signal paths connecting five input/output units (P1 to P5) and sixcircuit modules (M1 to M6) via (through-hole) the circuit moduleselection unit (SWA1 to SWA5 and SWB1 to SWB5) becomes the smallest.

The connection set may be determined so that the sum of delays of allsignal paths becomes the smallest within a range where the maximum valueof delays of all signal paths connecting five input/output units (P1 toP5) and six circuit modules (M1 to M6) via (through-hole) the circuitmodule selection unit (SWA1 to SWA5 and SWB1 to SWB5) does not exceedthe upper limit

By selecting the connection set so that the change of electriccharacteristics (particularly signal delay) along with connectionswitching becomes as small as possible in this way, the change of theperformance of the overall circuit along with fault repair can be keptsmall, therefore a semiconductor integrated circuit having the desiredperformance can be stably produced.

Fifth Embodiment

Next, a fifth embodiment of the present invention will be explained.

FIG. 5 is a diagram showing an example of the layout of input/outputunits (P1 to P5) and circuit modules (M1 to M6) in the semiconductorintegrated circuit shown in FIGS. 1A and 1B and omits illustration ofthe circuit module selection unit and the switch circuits included init. The input/output units and the circuit modules may be arranged infor example numerical order as shown in FIG. 5, but it is not alwaysnecessary to arrange these as shown in FIG. 5 when automaticallydesigning the layout and interconnects by CAD etc.

FIGS. 6A and 6B are diagrams showing an example of the layout andinterconnects of the input/output units (P1 to P5) and the circuitmodules (M1 to M6) in the semiconductor integrated circuit according tothe present embodiment. In the semiconductor integrated circuit shown inFIG. 6A, the input/output units (P1 to P5) are arranged in numericalorder in the same way as the example of FIG. 5, but the regular layoutas shown in the example of FIG. 5 is broken for the circuit modules (M1to M6). Note that the connections between the input/output units (P1 toP5) and the circuit modules (M1 to M6) are the same as the example ofFIG. 5.

FIGS. 7A to 7D are diagrams for explaining the routine of repair when afault occurs in the circuit module M3 in the semiconductor integratedcircuit shown in FIGS. 6A and 6B. In a default state before a fault isrepaired, as shown in FIG. 6B, input/output units Pi (i indicates aninteger from 1 to 5, same true below in the present embodiment) andcircuit modules Mi are connected in a one-to-one correspondence. In thisinitial connection, when a fault is discovered in the circuit module M3,first the circuit module M3 is disconnected from the input/output unitP3 (FIG. 7A). The circuit module M4 is connected to the input/outputunit P3 from which the circuit module M3 is disconnected in place ofthat. The circuit module M4 is disconnected from the input/output unitP5 (FIG. 7B). The circuit module M5 is connected to the input/outputunit P4 from which the circuit module M4 is disconnected in place ofthat. The circuit module M5 is disconnected from the input/output unitP5 (FIG. 7C). The input/output unit P5 disconnected from the circuitmodule M5 is connected to the circuit module M6 in the unconnected statein the initial connection (FIG. 7D). By the switching of connections asdescribed above, the input/output units P1, P2, P3, P4, and P5 and thecircuit modules M1, M2, M4, M5, and M6 are connected in a one-to-onecorrespondence, and the circuit module M3 having a fault is disconnectedfrom all input/output units. In this way, even in the case where thelayout and interconnects are not regular, the connections are the sameas those of the semiconductor integrated circuit shown in FIGS. 1A and1B and FIG. 5, therefore the fault repair can be carried out by the sameroutine.

FIGS. 8A and 8B are diagrams showing an example of the overall layout ofthe circuit. FIG. 8A shows an example of regularly arranging the generalcircuit block 100 and circuit module block (indicating a group ofcircuit modules which can replace each other's functions). In this case,inside the circuit module block, for example as shown in FIG. 5, thecircuit modules are arranged in numerical order at equal intervals. Thea regular layout is apt to reduce the variation of distances between theinput/output units and the circuit modules, therefore there is theadvantage that the change of the signal delay along with the connectionswitching can be kept very small, so this is suited to a case whereimportance is attached to the improvement of performance of the circuit.On the other hand, FIG. 8B shows an example where the general circuitblock 100 and the circuit module block are arranged in a free shape.This corresponds to for example the layout in the case of automaticallydesigning the layout and interconnects by CAD. As shown in FIG. 8B,overlapping of the region of the general circuit block and the region ofthe circuit module block is permitted. The circuit modules and theinput/output units can be freely arranged without being restricted tothe regularity as shown in FIG. 8A, therefore there is the advantagethat the density of layout of the circuit elements can be easily raised,so this is suitable for the case where importance is attached to thearea of the circuit.

When changing the viewpoint, it is also possible to regard thepreviously explained semiconductor integrated circuit shown in FIG. 4Cas the circuit obtained by changing the layout and interconnects of theinput/output units (P1 to P5) and the circuit modules (M1 to M6) in thesemiconductor integrated circuit shown in FIG. 4B. Namely, when theinput/output units P5, P1, P2, P3, and P4 in FIG. 4C are regarded as theinput/output units P1, P2, P3, P4 and P5 in FIG. 4B and the circuitmodules M6, M4, M1, M2, M3, and M5 in FIG. 4C are regarded as thecircuit modules M1, M2, M3, M4, M5, and M6 in FIG. 4B, the connectionsof the two are the same, but the layouts and interconnect patterns aredifferent.

Accordingly, it is also possible to employ the previously explainedstandard of the selection set as the standard when determining thelayout of the input/output units (P1 to P5) and the circuit modules (M1to M6) and interconnect paths. Namely, the layout of the input/outputunits (P1 to P5) and the circuit modules (M1 to M6) and interconnectpaths may be determined so that the maximum value of delays of allsignal paths connecting five input/output units (P1 to P5) and sixcircuit modules (M1 to M6) via (through-hole) the circuit moduleselection unit (SWA1 to SWA5 and SWB1 to SWB5) becomes the smallest.Alternatively, the layout of the input/output units (P1 to P5) and thecircuit modules (M1 to M6) and interconnect paths may be determined sothat the sum of delays of all signal paths connecting five input/outputunits (P1 to P5) and six circuit modules (M1 to M6) via (through-hole)the circuit module selection unit (SWA1 to SWA5 and SWB1 to SWB5)becomes the smallest. Alternatively, the layout of the input/outputunits (P1 to P5) and the circuit modules (M1 to M6) and interconnectpaths may be determined so that the sum of delays of all signal pathsconnecting becomes the smallest within the range where the maximum valueof delays of all signal paths connecting five input/output units (P1 toP5) and six circuit modules (M1 to M6) via (through-hole) the circuitmodule selection unit (SWA1 to SWA5 and SWB1 to SWB5) does not exceed apredetermined upper limit value.

Sixth Embodiment

Next, a sixth embodiment of the present invention will be explained.

The semiconductor integrated circuit according to the present embodimenthas a plurality of circuit module blocks. Here, a “circuit module block”designates a group of a plurality of (three or more) circuit moduleswhich can replace each other's functions. For example, in thesemiconductor integrated circuit shown in FIG. 1, the group of sixcircuit modules (M1 to M6) corresponds to one circuit module block.

Further, the semiconductor integrated circuit according to the presentembodiment, in the same way as that explained in the previousembodiments, has a circuit module selection unit having the function ofselecting part of the circuit modules from among the circuit moduleblocks and connecting the same to the input/output units of the generalcircuit block. The circuit module selection unit select parts of the(two or more) circuit modules from among the circuit module blocks inresponse to a control signal and connect the selected parts of thecircuit modules to the same number of input/output units in a one-to-onecorrespondence. Further, they connect one circuit module selected fromat least two circuit modules with respect to each input/output unitprovided in the general circuit block.

By providing the a plurality of circuit module blocks and circuit moduleselection units, it becomes possible to repair a greater number offaults in the semiconductor integrated circuit. For example, in thesemiconductor integrated circuit shown in FIG. 1, only one fault can berepaired, but by providing a plurality of the same circuit moduleblocks, it becomes possible to repair two or more faults.

Further, by providing a plurality of circuit module blocks, it becomespossible to repair a plurality of types of circuit modules. For example,there are a plurality of groups of circuit modules which can replaceeach other's functions, and circuit modules belonging to the samecircuit module group can replace each other's functions, but sometimescircuit modules belonging to the different circuit module groups cannotreplace each other's functions. In the a case, by configuring aplurality of circuit module blocks by adding redundant circuit modulesto each circuit module group and repairing faults in each of theseplurality of circuit module blocks, it becomes possible to repair aplurality of types of circuit modules.

Note that one circuit module may be included in only one circuit moduleblock or may be commonly used by a different plurality of circuit moduleblocks.

A circuit module commonly used by a plurality of circuit module blocksis provided with a function encompassing all or part of the functions ofthe other circuit modules included in the plurality of circuit moduleblocks. For example, a circuit module commonly used by a circuit moduleblock configured by circuit modules having the function A and by acircuit module block configured by circuit modules having the function Bhas a function C encompassing at least a part of the function A and atleast a part of the function B. For this reason, the commonly usedcircuit module can replace the functions of a circuit module included inany circuit module.

FIGS. 9A to 9C are diagrams showing an example where one circuit module(MC1) is commonly used by two circuit module blocks (B1, B2).

In the example of FIGS. 9A to 9C, the circuit module block B1 isconfigured by six circuit modules (M1 to M6) provided with the functionA and the circuit module MC1 provided with the function C. The circuitmodule block B2 is configured by six circuit modules (MB1 to MB6)provided with the function B and the circuit module MC1 provided withthe function C. Accordingly, the circuit module MC1 is commonly used bythe circuit module blocks B1 and B2.

The function C of the circuit module MC1 encompasses for example both ofthe function A of the circuit modules MA1 to MA6 and the function B ofthe circuit modules MB1 to MB6. Namely, the circuit module MC1 hasupward compatibility with respect to the circuit modules MA1 to MA6 andMB1 to MB6.

At the time of default, the circuit module MC1 having the upwardcompatibility is unconnected and becomes the redundant circuit module ofthe two circuit module blocks (B1, B2) (FIG. 9A). Further, the circuitmodules MA1, . . . , and MA6 of the circuit module block B1 areconnected to the input/output units P1, . . . , and P6 of the generalcircuit block in a one-to-one correspondence, and the circuit modulesMB1, . . . , and MB6 of the circuit module block B2 are connected to theinput/output units P7, . . . , and P12 of the general circuit block in aone-to-one correspondence.

If a fault occurs in for example the circuit module MA4 of the circuitmodule block B1 (FIG. 9B), the circuit module MA4 is disconnected fromthe input/output unit P4. Then, the circuit modules MA5, MA6, and MC1are connected to the input/output units P4, P5, and P6. Further, if afault occurs in for example the circuit module MB2 of the circuit moduleblock B2 (FIG. 9C), the circuit module MB2 is disconnected from theinput/output unit P8. Then, the circuit modules MC1 and MB1 areconnected to the input/output units P7 and P8. In this way, the circuitmodule MC1 having the upward compatibility can repair a fault of eitherof the circuit module blocks B1 and B2.

By providing a circuit module commonly used by a plurality of circuitmodule blocks, the number of redundant circuit modules solely providedfor each circuit module block can be decreased. For example, as shown inFIGS. 9A to 9C, even when there are no solely provided redundant circuitmodules, faults can be repaired by using the commonly used circuitmodule. For this reason, even in a case where for example the number ofcircuit module blocks is very large, since the redundant circuit modulesneed not be provided for each circuit module block, an unnecessaryincrease of the number of redundant circuit modules can be prevented.

FIGS. 10A and 10B are diagrams showing an example of the overall layoutof the circuit in the case where a plurality of circuit module blocksare provided. FIG. 10A shows an example of regular layout of circuitmodule blocks. In the example of the figures, the circuit module blocksare arranged in a matrix. Inside each circuit module block, in the sameway as for example the case of FIG. 8A, circuit modules are arranged innumerical order at equal intervals. The a regular layout has theadvantage that the change of the signal delay along with connectionswitching can be kept very small. On the other hand, FIG. 10B shows anexample where the circuit module blocks are arranged in a free shape andcorresponds to for example the layout in the case of automaticallydesigning the layout and interconnects by CAD. In the example of FIG.10B, the region of the general circuit block and the region of thecircuit module blocks overlap. The a free layout has the advantage thatthe layout density of the circuit elements is easily raised.

Seventh Embodiment

Next, a seventh embodiment of the present invention will be explained.

FIG. 11 is a diagram showing an example of the configuration of asemiconductor integrated circuit according to the seventh embodiment.The semiconductor integrated circuit according to the seventhembodiment, for example as shown in FIG. 11, has circuit modules M11 toM16 and M21 to M26, a general circuit block 100, switch circuits SWA11to SWA15 and SWA21 to SWA25, switch circuits SWB11 to SWB15 and SWB21 toSWB25, a control unit 110, and a power supply switch unit 120.

The group of circuit modules M11 to M16 and the group of M21 to M26 areembodiments of the circuit module blocks of the claims. The generalcircuit block 100 is an embodiment of the circuit block of the claims.The circuits including the switch circuits SWA11 to SWA15, SWA21 toSWA25, SWB11 to SWB15, and SWB21 to SWB25 are embodiments of the circuitmodule selection unit of the claims. The group of switch circuits SWA11to SWA15 and the group of the switch circuits SWA21 to SWA25 areembodiments of the first switch group of the claims. The group of theswitch circuits SWB11 to SWB15 and the group of the switch circuitsSWB21 to SWB25 are embodiments of the second switch group of the claims.The circuit modules M11 to M16 and M21 to M26 are sets of circuitshaving a predetermined function in the same way as the previouslyexplained circuit modules M1 to M6 (FIGS. 1A and 1B). The group of thecircuit modules M11 to M16 and the group of circuit modules M11 to M16form circuit module blocks. In the present embodiment, the group of thecircuit modules M11 to M16 will be called a “first circuit moduleblock”, and the group of the circuit modules M21 to M26 will be called a“second circuit module block”. The circuit modules belonging to the samecircuit module block can replace each other's functions. The circuitmodules belonging to different circuit module blocks may be able to orunable to replace each other's functions.

The general circuit block 100 has input/output units P11 to P15 forexchanging signals with the first circuit module block (M11 to M16) andinput/output units P21 to P25 for exchanging signals with the secondcircuit module block (M21 to M26) and executes the predeterminedprocessing in cooperation with these circuit modules.

Each of the input/output units P11 to P15 outputs at least one signal toone circuit module belonging to the first circuit module block (M11 toM16) and, at the same time, receives as input at least one signalgenerated in the one circuit module. Each of the input/output units P21to P25 outputs at least one signal to one circuit module belonging tothe second circuit module block (M21 to M26) and, at the same time,receives as input at least one signal generated in the one circuitmodule.

A switch circuit SWA1 i (i indicates an integer from 1 to 5, same truebelow in the present embodiment) is connected between an input/outputunit P1 i and a circuit module M1 i and turns on or off in response to acontrol signal supplied from the control unit 110. A switch circuit SWA2i is connected between an input/output unit P2 i and a circuit module M2i and turns on or off in response to a control signal supplied from thecontrol unit 110. A switch circuit SWB1 i is connected between theinput/output unit P1 i and a circuit module M1(i+1) and turns on or offin response to a control signal supplied from the control unit 110. Aswitch circuit SWB2 i is connected between the input/output unit P2 iand a circuit module M2(i+1) and turns on or off in response to acontrol signal supplied from the control unit 110.

The switch circuits SWA11 to SWA15 and SWB11 to SWB15 have the functionof selecting five circuit modules from the first circuit module block(M11 to M16) and connecting the same with the input/output units P11 toP15 in a one-to-one correspondence. In the present embodiment, thecircuit configured by these switch circuits SWA11 to SWA15 and SWB11 toSWB15 will be called a “first circuit module selection unit”. The firstcircuit module selection unit (SWA11 to SWA15 and SWB11 to SWB15)connects one circuit module selected from two circuit modules includedin the first circuit module block (M11 to M16) to each of theinput/output units P11 to P15. Namely, it selects one of the circuitmodule M1 i or the circuit module M1(i+1) in response to a controlsignal supplied from the control unit and connects this selected circuitmodule to the input/output unit P1 i.

The switch circuits SWA21 to SWA25 and SWB21 to SWB25 have the functionof selecting five circuit modules from the second circuit module block(M21 to M26) and connecting the same with the input/output units P21 toP25 in a one-to-one correspondence. In the present embodiment, thecircuit configured by these switch circuits SWA21 to SWA25 and SWB21 toSWB25 will be called a “second circuit module selection unit”. Thesecond circuit module selection unit (SWA21 to SWA25 and SWB21 to SWB25)connects one circuit module selected from two circuit modules includedin the second circuit module block (M21 to M26) to each of theinput/output units P21 to P25. Namely, it selects one of the circuitmodule M2 i or the circuit module M2(i+1) in response to a controlsignal supplied from the control unit and connects this selected circuitmodule to the input/output unit P2 i.

The control unit 110 generates a control signal for selecting fivecircuit modules from the first circuit module block (M11 to M16) and thesecond circuit module block (M21 to M26) so as to disconnect the faultycircuit module (circuit module previously provided for redundancy whenthere is no fault) from all input/output units and supplies this to thefirst circuit module selection unit and the second circuit moduleselection unit explained above.

Note that the control unit 110 commonly uses the control signal suppliedto the first circuit module selection unit (SWA11 to SWA15 and SWB11 toSWB15) and the second circuit module selection unit (SWA21 to SWA25 andSWB21 to SWB25), therefore, when a specific circuit module isdisconnected from the input/output units in the first circuit moduleblock (M11 to M16), a specific circuit module corresponding to this isdisconnected from the input/output units in the second circuit moduleblock (M21 to M26).

This will be explained in more generalized terms. In the overall set ofthe circuit modules (M11 to M16 and M21 to M26), six partial sets areformed. Each of these six partial sets is configured by two circuitmodules. These sets do not have any relation with each other. Whendesignating the six partial sets as the first partial set to the sixthpartial set, the partial sets include the following components.

First partial set . . . {M11, M21}

Second partial set . . . {M12, M22}

Third partial set . . . {M13, M23}

Fourth partial set . . . {M14, M24}

Fifth partial set . . . {M15, M25}

Sixth partial set . . . {M16, M26}

The control unit 110 generates a control signal so as to disconnect allcircuit modules belonging to the partial set from the input/output unitswhen the circuit module belonging to a certain partial set isdisconnected from the input/output units. For example, when the circuitmodule M23 is disconnected from the input/output units, a control signalis generated so that the circuit module M13 belonging to the partial setthe same as this is disconnected from the input/output units. Namely,circuit modules belonging to the same partial set are controlled inconnection state with the input/output units by the same control signalsupplied from the control unit 110.

Here, the state of each switch circuit in a case where a control signaldesignating disconnection of an n-th partial set (n indicates an integerfrom 1 to 6, same true below in the present embodiment) from allinput/output units is generated in the control unit 110 will beexplained. In this case, when n is an integer from 2 to 5 (that is, whenthe second to the fifth partial sets are to be disconnected), the switchcircuits SWA11 to SWA1 (n−1) and SWA21 to SWA2(n−1) turn on, and theswitch circuits SWA1 n to SWA15 and SWA2 n to SWA25 turn off. Further,the switch circuits SWB11 to SWB1(n−1) and SWB21 to SWB2(n−1) turn off,and the switch circuits SWB1 n to SWB15 and SWB2 n to SWB25 turn on.When n is the integer 1 (that is, when the first partial set is to bedisconnected), all of the switch circuits SWA11 to SWA15 and SWA21 toSWA25 turn off, and all of the switch circuits SWB11 to SWB15 and SWB21to SWB25 turn on. When n is the integer 6 (that is, when the firstpartial set is to be disconnected), all of the switch circuits SWA11 toSWA15 and SWA21 to SWA25 turn on, and the switch circuits SWB11 to SWB15and SWB21 to SWB25 turn off.

The power supply switch unit 120 shuts off the power to any partial setdisconnected from the input/output units among the first partial set tothe sixth partial set in response to a control signal of the controlunit 110. For example, the power supply switch unit 120 has six powersupply switch circuits (not shown) inserted in the power supply lines ofthe first partial set to the sixth partial set. When a certain partialset is disconnected from the input/output units, the power supply switchunit inserted in that power supply line turns off.

FIG. 12 shows the connection state in a case where a fault occurs in thecircuit module M23. In this case, the control unit 110 generates acontrol signal so as to disconnect the circuit module M23 from allinput/output units. Upon receipt of this control signal, the switchcircuits SWA11, SWA12, SWA21, and SWA22 turn on, the switch circuitsSWA13, SWA14, SWA15, SWA23, SWA24, and SWA25 turn off, the switchcircuits SWB11, SWB12, SWB21, and SWB22 turn off, and the switchcircuits SWB13, SWB14, SWB15, SWB23, SWB24, and SWB25 turn on. Due tothis, the input/output units P11 and P21 are connected with the circuitmodules M11 and M21, the input/output units P12 and P22 are connectedwith the circuit modules M12 and M22, the input/output units P13 and P23are connected with the circuit modules M14 and M24, the input/outputunits P14 and P24 are connected with the circuit modules M15 and M25,and the input/output units P15 and P25 are connected with the circuitmodules M16 and M26, and the circuit modules M13 and M23 aredisconnected from the general circuit block 100.

By the semiconductor integrated circuit according to the presentembodiment, the connection states of all circuit modules belonging tothe same partial set are commonly controlled by the same control signalsupplied from the control unit 110. Due to this, it is possible togreatly decrease the number of control signals, and the circuitconfiguration of the control unit 110 can be simplified, in comparisonwith the case where the connection states with the input/output unitsare independently controlled for individual circuit modules.

The supply of power to the partial set disconnected from theinput/output units is shut off, therefore wasted consumption of power incircuit modules not contributing to the operation of the circuit can beprevented. When a fault causing a large current to flow in the powersupply line occurs in a circuit module, this is cut off and theinfluence upon the power supply system and other circuits can beprevented, therefore the drop of the yield due to a fault of a circuitmodule can be effectively suppressed.

When inspecting for faults, it is sufficient to inspect for the presenceof faults for each partial set, therefore the inspection time can beshortened in comparison with the case of inspecting individual circuitmodules.

Further, when writing information of a faulty circuit module into thesemiconductor integrated circuit by utilizing a fuse or other storageelement, since the information of the presence of faults may be writtenfor each partial set, the amount of information becomes smaller and thetime required for the write processing can be shortened.

In the semiconductor integrated circuit according to the presentembodiment, when there is a faulty circuit module, all circuit modulesbelonging to the partial set the same as this are disconnected from theinput/output units, therefore the normal circuit modules also becomewasted. For this reason, if the probability of occurrence of faults ishigh, the number of circuit modules which become wasted tends to becomelarger. However, if the probability of occurrence of faults is not sohigh a large amount of circuit modules of relatively small scale areprovided, the circuit area necessary for achieving the same yield can besuppressed in comparison with the method of control of the connectionstate for individual circuit modules and the control of shutoff of thepower supply.

Eighth Embodiment

Next, an eighth embodiment of the present invention will be explained.

In the semiconductor integrated circuit shown in FIGS. 1A and 1B, thecircuit module to be connected to each input/output unit is selectedfrom two circuit modules, but in the semiconductor integrated circuitaccording to the present embodiment, this is selected from among threeor more circuit modules.

FIG. 13A is a diagram showing an example of the configuration of asemiconductor integrated circuit selecting the circuit module connectedto each input/output unit from among three circuit modules.

The semiconductor integrated circuit shown in FIG. 13A has a generalcircuit block provided with input/output units P1 to P5, circuit modulesM1 to M7, and a circuit module selection unit. Note that, in FIG. 13A to13C and FIGS. 14A to 14C explained later, the connection paths betweeninput/output units and circuit modules are shown, but illustration ofthe circuit module selection unit realizing this switching of connectionpaths is omitted.

The input/output unit Pi (i indicates an integer from 1 to 5, same truebelow in the explanation of FIGS. 13A to 13C) is connected to one ofcircuit modules Mi, M(i+1), or M(i+2). These connections are switched bythe circuit module selection unit.

FIG. 13B shows an example of the initial connection pattern in a casewhere there are no faults in the circuit modules M1 to M7. In theexample shown in FIG. 13B, the input/output units P1, P2, P3, P4, and P5and the circuit modules M2, M3, M4, M5, and M6 are connected in aone-to-one correspondence.

FIG. 13C shows the connection pattern in a case where the circuitmodules M2 and M4 fail. In the example of FIG. 13C, the input/outputunits P1, P2, P3, P4, and P5, and the circuit modules M1, M3, M5, M6,and M7 are connected in a one-to-one correspondence, and the circuitmodules M2 and M4 are disconnected from the input/output units.

When the initial connection pattern is set as shown in FIG. 13B, theconnection pattern for repairing the faults can be determined accordingto for example the following routine. First, the presence of any faultsis sequentially judged from the circuit module M1 to M7 (that is, towardthe right direction in the figure). If there is a faulty circuit module,this is disconnected from the input/output units. Then, the otherparties of connection of the input/output units on the left side in thefigure from this disconnected input/output unit are wholly shiftedtoward the left direction in the figure. Further, when the above shiftis carried out, the presence of faults is sequentially judged from thecircuit module M7 to M1 (that is, toward the left direction in thefigure). If there is a faulty circuit module different from thepreviously explained circuit module, this is disconnected from theinput/output units. Then, the other parties of connection of theinput/output units on the right side in the figure from thisdisconnected input/output unit are wholly shifted toward the rightdirection in the figure. For example, in the example of FIG. 13C, theother party of connection of the input/output unit existing on the leftside from the input/output unit P1 connected to the faulty circuitmodule M2 (that is, the input/output unit P1) is shifted toward the leftdirection in the figure. Further, the other party of connection of theinput/output units existing on the right side from the input/output unitP3 connected to the faulty circuit module M4 (that is, the input/outputunits P3, P4, P5) are shifted toward the right direction in the figure.

FIG. 14A is a diagram showing an example of the configuration of asemiconductor integrated circuit selecting a circuit module connected toeach input/output unit from among four circuit modules. Thesemiconductor integrated circuit shown in FIG. 14A has a general circuitblock provided with input/output units P1 to P3, circuit modules M1 toM4, and a circuit module selection unit.

The input/output unit P1 is connected to one of the circuit modules M1,M2, M4, and M5. The input/output unit P2 is connected to one of thecircuit modules M2, M3, M4, and M5. The input/output unit P3 isconnected to one of the circuit modules M1, M2, M3, and M4. Theinput/output unit P4 is connected to one of the circuit modules M1, M2,M3, and M4. These connections are switched by the circuit moduleselection unit.

FIG. 14B shows an example of the initial connection pattern when thereis no fault in the circuit modules M1 to M4. In the example shown inFIG. 14B, the input/output units P1, P2, and P3 and the circuit modulesM5, M4, and M2 are connected in a one-to-one correspondence.

FIG. 14C shows the connection pattern when the circuit module M2 fails.In the example of FIG. 14C, the input/output units P1, P2, and P3 andthe circuit modules M5, M4, and M1 are connected in a one-to-onecorrespondence, and the circuit module M2 is disconnected from eachinput/output unit.

Next, the general routine for searching for a connection pattern forrepairing a fault in the semiconductor integrated circuit according tothe present embodiment will be explained with reference to the flowcharts of FIG. 15 to FIG. 17.

Step ST100

First, the connection pattern of the input/output units and circuitmodules in the semiconductor integrated circuit to be inspected is setto for example a predetermined initial pattern as shown in FIG. 13B andFIG. 14B.

Step ST105

Then, the presence of any fault in the circuit modules is inspected forin the connection pattern set in the semiconductor integrated circuit atpresent. For example, the operation of each circuit module connected toan input/output unit is inspected by using for example a scan path testor other inspection technique.

Step ST110

When the inspection at step ST105 does not find any fault, it is judgedthat the semiconductor integrated circuit being inspected passes and thesearch of the connection pattern ends. In this case, the connectionpattern set at present is acquired as a search result.

Step ST115

When any faulty circuit modules are found, it is judged whether or notthe number of the faulty circuit modules is larger than the number ofredundant circuit modules. If it is larger, the faults cannot berepaired, therefore it is judged that the semiconductor integratedcircuit being inspected is defective and the search of the connectionpattern ends. When the number of faulty circuit modules is smaller thanthe number of redundant circuit modules or the two are equal, there is apossibility that the faults can be repaired, therefore the searchprocessing of the connection pattern is executed at step ST120.

Steps ST125 and ST130

As a result of the search processing at step ST120, when a patternconnecting circuit modules not judged as faulty to the input/outputunits one by one is found, the connection pattern of the semiconductorintegrated circuit being inspected is set to this retrieved connectionpattern and the inspection of step ST105 is executed again.

FIG. 16 and FIG. 17 are flow charts for explaining the search processingof the connection pattern at step ST120. Note that the change of theconnection pattern carried out in this search processing is a virtualchange for searching for the target connection pattern and not actuallycarried out in the semiconductor integrated circuit being inspected.This search processing is executed by for example software on acomputer.

Step ST200

First, the faulty circuit module found by the inspection at step ST105is disconnected from all input/output units. Note that, in FIG. 16 andFIG. 17, an input/output unit is described as “I/O”.

Step ST205

Next, it is judged whether or not there is any unconnected input/outputunit which is not connected to a circuit module in the presentconnection pattern. When there is no unconnected input/output unit, thepresent connection pattern is acquired as the search result, and thesearch processing ends.

Step ST210

When it is judged at step ST205 that there is an unconnectedinput/output unit, the number i (i indicates a natural number, same truebelow in the explanation of FIG. 16 and FIG. 17) indicating aregistration order of input/output units is set at the initial value“1”. Further, the registrations of input/output units (step ST250) andthe registrations of circuit modules (step ST310) are all initializedand brought to the unregistered state. Note that, the “registration”carried out for the input/output units and circuit modules will beexplained in the later steps.

Step ST215

The input/output unit unconnected at present is registered as the i-thinput/output unit. When there are a plurality of unconnectedinput/output units, any one is selected from among those and defined asthe i-th input/output unit.

Step ST220

Circuit modules satisfying all of the following four conditions aresearched for:

(1) Able to be connected to the i-th input/output unit.

(2) Judged not faulty in the inspection of step ST105

(3) Not connected to the first to the (i−1)th input/output units (thatis, already registered input/output units) in a case where the number iis 2 or more.

(4) Not registered as a connection prohibited circuit module withrespect to the i-th input/output unit.

Step ST225

When circuit modules satisfying the conditions of step ST220 are found,the routine shifts to step ST230, while when they are not found, theroutine shifts to step ST300.

Step ST230

One circuit module satisfying the conditions of step ST200 is selected.

Step ST235

The circuit module selected at step ST230 is connected to the i-thinput/output unit.

Step ST240

It is judged if an input/output unit different from the i-thinput/output unit is connected to the circuit module selected at stepST230. When a different input/output unit is connected, the routineshifts to step ST245, while when it is not connected, the routinereturns to step ST205.

Step ST245

“1” is added to the number i and the routine shifts to step ST250.

Step ST250

The different input/output unit connected to the circuit module selectedat step ST230 is disconnected from the circuit module. Further, theinput/output unit disconnected from the circuit module is registered asthe i-th input/output unit, and the circuit module search of step ST220is carried out again.

Step ST300

When the circuit module satisfying the conditions is not found by thesearch of step ST220, it is judged if the present number i is “1”.Namely, it is judged if the present i-th input/output unit is theinput/output unit registered first after the initialization of theregistration of step ST210. If it is that input/output unit, it can beconsidered that any circuit module which can be connected to the firstinput/output unit does not satisfy the condition (2) of step ST220 (thatis, there is a fault), therefore a circuit module having a fault will beconnected to the first input/output unit no matter what connectionpattern is employed. For this reason, in this case, it is judged thatthe search of the connection pattern has failed and the searchprocessing ends.

Steps S305, ST310, and ST315

When it is judged that the present number i is not “1” at step ST300,the circuit module is disconnected from the (i−1)th input/output unitregistered one time before the present i-th input/output unit, and thisdisconnected circuit module is connected to the i-th circuitmodule-again. Then, the circuit module disconnected from this (i−1)thinput/output unit is registered as a connection prohibited circuitmodule with respect to the (i−1)th input/output unit. Further, theregistration of the present i-th input/output unit is erased, and thestate is returned back to the unregistered state. By the aboveprocessing (ST305, ST310, and ST315), the present connection patternreturns to the state where the (i−1)th input/output unit wasunconnected.

Step ST320

“1” is subtracted from the number i, and the circuit module search ofstep ST220 is carried out again.

Here, a specific example of the connection pattern search processingshown in FIG. 16 and FIG. 17 will be explained with reference to FIGS.18A to 18C.

At step ST250, an input/output unit Pb is registered as the 10thinput/output unit (FIG. 18A). At this time, the number i is “10”.

There are four circuit modules (Me, Mf, Mg, Mh) which can be connectedto the input/output unit Pb. Among these, the circuit modules Me and Mfare connected to the already registered input/output units (Pa, Pe),therefore the condition of (3) explained above is not satisfied. Thecircuit modules Mg and Mh satisfy all of the conditions (1) to (4).Therefore, at step ST220, two circuit modules (Mg, Mh) are retrieved.

At step ST230, the circuit module Mg between these two circuit modules(Mg, Mh) is selected. The circuit module Mg is connected to theinput/output unit Pb at step ST235. Here, the input/output unit Pc isconnected to the circuit module Mg, therefore the input/output unit Pcis disconnected from the circuit module Mg at step ST250, and theinput/output unit Pc which becomes unconnected is registered as the 11thinput/output unit (FIG. 18B). At this time, the number i is “11”.

There are two circuit modules (Mf, Mm) which can be connected to theinput/output unit Pc. Among these, the circuit module Mf is connected tothe already registered input/output units (Pa, Pe), therefore thecondition of (3) explained above is not satisfied. Namely, there is nocircuit module satisfying the conditions of step ST220. For this reason,the processing shifts from step ST225 to step ST300.

At this time, the number i is “11”, therefore the processing shifts fromstep ST300 to step ST305.

At step ST305, the circuit module Mg is disconnected from theinput/output unit Pb as the 10th input/output unit. This disconnectedcircuit module Mg is connected to the original input/output unit Pc.Further, at step ST310, the circuit module Mg disconnected from theinput/output unit Pb is registered as the connection prohibited circuitmodule with respect to the input/output unit Pb. Then, at step ST315,the registration of the 11th input/output unit is erased, and theunregistered state is exhibited for the 11th input/output unit.

When the processing of steps ST305, ST310, and ST315 returns to theconnection pattern shown in FIG. 18A, the number i is subtracted from“11” to “10” at step ST320, then the search of the circuit modules iscarried out again at step ST220.

Among the four circuit modules (Me, Mf, Mg, Mh) to which theinput/output unit Pb can be connected, the circuit modules Me and Mf donot satisfy the condition (3), and the circuit module Mg does notsatisfy the condition (4). Only the circuit module Mh satisfies all ofthe conditions (1) to (4). Therefore, at step ST220, only the circuitmodule Mh is retrieved.

At step ST230, this circuit module Mh is selected. The circuit module Mhis connected to the input/output unit Pb at step ST235. Here, theinput/output unit Pd is connected to the circuit module Mh, thereforethe input/output unit Pd is disconnected from the circuit module Mh atstep ST250, and the input/output unit Pd which becomes unconnected isregistered as the 11th input/output unit (FIG. 18C).

By the semiconductor integrated circuit according to the presentembodiment, by increasing the number of circuit modules which can beselectively connected with respect to one input/output unit to three ormore, the patterns connecting input/output units and circuit modules ina one-to-one correspondence can be increased, therefore it becomespossible to flexibly repair faults occurring in a variety of manners.Further, by the increase of the connection patterns, even when thestructure becomes complex, a connection pattern for circumventing thefaults can be found according to the routine as shown in FIG. 16 andFIG. 17.

Ninth Embodiment

Next, a ninth embodiment of the present invention will be explained.

FIG. 19 is a diagram showing an example of the configuration of thesemiconductor integrated circuit according to the ninth embodiment. Thesemiconductor integrated circuit according to the present embodiment,for example as shown in FIG. 19, has circuit modules M101 to M108, M201to M208, M301 to M308, M401 to M408, and M501, a bus 10, bridge circuits21 to 24, switch networks 31 to 34, a universal serial bus (USB)interface circuit 41, a double data rate dynamic random access memory(DDR DRAM) interface circuit 42, direct memory access (DMA) controllers43 to 45, a supervisor processor 47, a co-processor 46, a secondarycache 48, and a circuit module selection unit 50. Further, thesemiconductor integrated circuit according to the present embodiment hasa control unit 60, storage unit 70, and signal input unit 80 as shown inFIG. 21 explained later as components according to the switching controlof circuit modules.

The circuit modules M101 to M108, M201 to M208, M301 to M308, M401 toM408, and M501 are sets of circuits each having predetermined functionsand which can replace each other's functions.

Each circuit module, for example as shown in FIG. 20, has a transfercontrol unit 101, operation unit 103, and storage unit 102.

The transfer control unit 101 controls the transfer of the datainput/output via (through-hole) the input/output units (P101, P102, . .. ) of the switch networks 31 to 34. The operation unit 103 executes anoperation in accordance with command codes stored in the storage unit102. The operation unit 103, for example, mounts an arithmetic logicalunit (ALU) and sequencer circuit. The sequencer circuit controls the ALUin response to the above command codes to execute various operations.The storage unit 102 stores the command codes executed in the operationunit 103, the data utilized for the processing of the operation unit103, the data output from the operation unit 103, etc. as processingresults. Further, it temporarily stores the data input/output at thetransfer control unit 101.

The circuit module shown in FIG. 20 executes processing according to thegroup of command codes supplied through for example the input/outputunits of the switch networks 31 to 34. The group of command codes istransferred from the supervisor processor 47 etc. directed to theindividual input/output units, therefore, when the connection betweenthe input/output units and circuit modules is switched by the circuitmodule selection unit 50 explained later, different groups of commandcodes will be supplied to the circuit modules. For this reason, theprocessing function of the circuit module changes in accordance with theinput/output unit as the destination of connection.

Each of the switch networks 31 to 34 has eight input/output unitsconnected to circuit modules. Namely, the switch network 31 has theinput/output units P101 to P108, the switch network 32 has theinput/output units P201 to P208, the switch network 33 has theinput/output units P301 to P308, and the switch network 34 has theinput/output units P401 to P408. The switch networks 31 to 34 connecteight input/output units to each other so that the circuit modules canexchange data with respect to each other. Further, they connect bridgecircuits and input/output units so that the circuit modules can exchangedata with units (41 to 47) on the bus 10 via (through-hole) the bridgecircuits (21, 22, . . . )

The bridge circuits 21 to 24 are controlled to transfer data to eachother between the switch networks 31 to 34 and the bus 10.

The bus 10 is controlled so that circuit modules of the switch networks31 to 34 connected via (through-hole) the bridge circuits 21 to 24 andunits such as the supervisor processor 47 can transfer data to eachother.

The bus configured by the switch networks 31 to 34, the bridge circuits21 to 24, and the bus 10 may be of any structure. For example, it may bebased on for example the advanced extensible interface (AXI) or otherbus standard.

The bus 10 has the USB interface circuit 41, the DDR DRAM interfacecircuit 42, the DMA controllers 43 to 45, the supervisor processor 47,and the co-processor 46 connected to it. The USB interface circuit 41 iscontrolled to communicate with the USB apparatus. The DDR DRAM interfacecircuit 42 is controlled so that each unit connected to the bus 10accesses the DDR DRAM. The DMA controllers 43 to 45 perform control fortransferring data by DMA between units connected to the bus 10. ThreeDAM controllers independently transfer data of the three channels. Thesupervisor processor 47 centrally controls the entire operation of thesystem. The secondary cache 48 is connected to the supervisor processor47 and temporarily stores data having a high usage frequency. Theco-processor 46 assists the operation and processing in the supervisorprocessor 47.

The circuit module selection unit 50 selects 32 circuit modules fromamong 33 circuit modules (M101 to M108, M201 to M208, M301 to M308, M401to M408, M501) in response to the control signal supplied from thecontrol unit 60 and connects these to 32 input/output units (P101 toP108, P201 to P208, P301 to P308, P401 to P408) in a one-to-onecorrespondence. Further, one circuit module selected from two circuitmodules in response to the above control signal is connected to each of32 input/output units.

Here, the circuit module selection unit 50 and the portion concernedwith the control thereof will be explained with reference to FIG. 21.Note that, for the convenience of explanation, in FIG. 21, the notationsof circuit modules and input/output units are replaced as follows:

(Circuit Modules)

M101, . . . , M108→M1, . . . , M8;

M208, . . . , M201→M9, . . . , M16;

M301, . . . , M308→M17, . . . , M24;

M408, . . . , M401→M26, . . . , M33;

M501→M25;

(Input/Output Units)

P101, . . . , P108→P1, . . . , P8;

P208, . . . , P201→P9, . . . , P16;

P301, . . . , P308→P17, . . . , P24;

P408, . . . , P401→P25, . . . , P32;

The circuit module selection unit 50, for example as shown in FIG. 21,has switch circuits SWA1 to SWA32 and switch circuits SWB1 to SWB32. Thegroup of the switch circuits SWA1 to SWA32 is an embodiment of the firstswitch group of the present invention. The group of the switch circuitsSWB1 to SWB32 is an embodiment of the second switch group of the presentinvention.

The switch circuit SWAi (i indicates an integer from 1 to 32, same truebelow in the present embodiment) is connected between the input/outputunit Pi and the circuit module Mi, turns on when a control signal Scisupplied from the control unit 60 has the value “0”, and turns off whenthe control signal Sci has the value “1”.

The switch circuit SWBi is connected between the input/output unit Piand the circuit module M(i+1), turns off when the control signal Sci hasthe value “0”, and turns on when the control signal Sci has the value“1”.

The switch circuit SWAi has at least one circuit for turning on/off asignal Sin transmitted from the input/output unit Pi to the circuitmodule Mi and at least one circuit for turning on/off a signal Souttransmitted from the circuit module Mi to the input/output unit Pi. Inthe same way, the switch circuit SWBi has at least one circuit forturning on/off the signal Sin transmitted from the input/output unit Pito the circuit module M(i+1) and at least one circuit for turning on/offthe signal Sout transmitted from the circuit module M(i+1) to theinput/output unit Pi. Below, the circuits for turning on/off individualsignals will be called switch elements. Some examples of theirconfigurations thereof will be explained below.

FIG. 22 is a diagram showing a first example of the configuration ofswitch elements for turning on/off a signal transmitted from aninput/output unit to a circuit module.

A switch element SE1 shown in FIG. 22 is a circuit for turning on/off asignal Sin1 transmitted from the input/output unit Pi to the circuitmodule Mi and is included in the switch circuit SWAi. The switch elementSE1 has an input terminal Ti for receiving as input the signal from theinput/output unit Pi and an output terminal To for outputting the signalto the circuit module Mi. When the control signal Sci has the value “0”(low level), the signal input to the input terminal Ti is logicallyinverted and output from the output terminal To, while when the controlsignal Sci has the value “1” (high level), the output terminal To isbrought to a high impedance state.

A switch element SE2 shown in FIG. 22 is a circuit for turning on/off asignal Sin2 transmitted from the input/output unit Pi to the circuitmodule Mi(i+1) and is included in the switch circuit SWBi. The switchelement SE2 has an input terminal Ti for receiving as input the signalfrom the input/output unit Pi and an output terminal To for outputtingthe signal to the circuit module Mi(i+1). When the control signal Scihas the value “1” (high level), the signal input to the input terminalTi is logically inverted and output from the output terminal To, whilewhen the control signal Sci has the value “0” (low level), the outputterminal To is brought to the high impedance state. Further, the switchelement SE2 connects the output terminal To to the ground line VSS whena signal designating disconnection of the circuit module (i+1) as thedestination of connection from all input/output units is input.

Both of the switch elements SE1 and SE2 have four transistors (Q1 toQ4). The p-type MOS transistors Q1 and Q2 are connected in seriesbetween the power supply line VCC and the output terminal To, and then-type MOS transistors Q3 and Q4 are connected in series between theoutput terminal To and the ground line VSS. Gates of the p-type MOStransistors Q1 and Q4 receive as input a signal SMin1 from theinput/output unit Pi.

In the switch element SE1, the control signal Sci is input to the gateof the p-type MOS transistor Q2. A control signal /Sci obtained byinverting the logic of the control signal Sci in a not shown invertercircuit is input to the gate of the n-type MOS transistor Q3. On theother hand, in the switch element SE2, the control signal /Sci obtainedby inversion of the logic explained above is input to the gate of thep-type MOS transistor Q2, and the control signal Sci is input to thegate of the n-type MOS transistor Q3.

When the control signal Sci is at the low level (value “0”), in theswitch element SE1, the p-type MOS transistor Q2 and the n-type MOStransistor Q3 turn on, therefore the switch element SE1 operates as aninverter circuit. The signal SMin1 from the input/output unit Pi islogically inverted by this inverter circuit and input to the circuitmodule Mi. Further, in the switch element SE2, the p-type MOS transistorQ2 and the n-type MOS transistor Q3 turn off, the output terminal Tobecomes the high impedance state, and the circuit module M(i+1) and theinput/output unit Pi are disconnected. When the control signal Sci is atthe high level (value “1”), the switch element SE2 operates as aninverter circuit reverse to that explained above. The signal SMin1 fromthe input/output unit Pi is logically inverted by this inverter circuitand input to the circuit module M(i+1). Further, in the switch elementSE1, the output terminal To becomes the high impedance state, and thecircuit module Mi and the input/output unit Pi are disconnected.

FIG. 23 is a diagram showing a first example of configuration of theswitch elements for turning on/off a signal transmitted from a circuitmodule to an input/output unit. A switch element SE3 shown in FIG. 23 isa circuit for turning on/off the signal Sout1 transmitted from thecircuit module Mi to the input/output unit Pi and is included in theswitch circuit SWAi.

The switch element SE3 has an input terminal Ti for receiving as input asignal from the circuit module Mi and an output terminal To foroutputting a signal to the input/output unit Pi. When the control signalSci has the value “0” (low level), the signal input to the inputterminal Ti is logically inverted and output from the output terminalTo, while when the control signal Sci has the value “1” (high level),the output terminal To is brought to the high impedance state.

A switch element SE4 shown in FIG. 23 is a circuit for turning on/offthe signal Sout2 transmitted from the circuit module M(i+1) to theinput/output unit Pi and included in a switch circuit SWBi. The switchelement SE4 has an input terminal Ti for receiving as input a signalfrom the circuit module M(i+1) and an output terminal To for outputtinga signal to the input/output unit Pi. When the control signal Sci hasthe value “1” (high level), the signal input to the input terminal Ti islogically inverted and output from the output terminal To, while whenthe control signal Sci has the value “0” (low level), the outputterminal To is brought to the high impedance state.

The switch elements SE3 and SE4 have four transistors (Q1 to Q4) in thesame way as the switch elements SE1 and SE2. The p-type MOS transistorsQ1 and Q2 are connected in series between the power supply line VCC andthe output terminal To, while the n-type MOS transistors Q3 and Q4 areconnected in series between the output terminal To and the ground lineVSS.

In the switch element SE3, the control signal Sci is input to the gateof the p-type MOS transistor Q2, the control signal /Sci is input to thegate of the n-type MOS transistor Q3, and the signal Sout1 from thecircuit module Mi is input to gates of the p-type MOS transistors Q1 andQ4. On the other hand, in the switch element SE4, the control signal/Sci is input to the gate of the p-type MOS transistor Q2, the controlsignal Sci is input to the gate of the n-type MOS transistor Q3, and thesignal Sout2 from the circuit module M(i+1) is input to the gates of thep-type MOS transistors Q1 and Q4.

When the control signal Sci is at the low level (value “0”), the p-typeMOS transistor Q2 and the n-type MOS transistor Q3 turn on in the switchelement SE3, and the switch element SE3 operates as the invertercircuit. The signal Sout1 from the circuit module Mi is logicallyinverted by this inverter circuit and input to the input/output unit Pi.Further, in the switch element SE4, the p-type MOS transistor Q2 and then-type MOS transistor Q3 turn off, the output terminal To becomes thehigh impedance state, and the circuit module M(i+1) and the input/outputunit Pi are disconnected. When the control signal Sci is at the highlevel (value “1”), the switch element SE4 operates as the invertercircuit reverse to that explained above. The signal Sout2 from thecircuit module (i+1) is logically inverted at this inverter circuit andinput to the input/output unit Pi. In the switch element SE3, the outputterminal To becomes the high impedance state, and the circuit module Miand the input/output unit Pi are disconnected.

FIG. 24 is a diagram showing a second example of the configuration ofthe switch elements for turning on/off a signal transmitted from aninput/output unit to a circuit module.

A switch element SE1A shown in FIG. 24 is a circuit for turning on/offthe signal Sin1 transmitted from the input/output unit Pi to the circuitmodule Mi in the same way as the switch element SE1 shown in FIG. 22 andis included in the switch circuit SWAi. The switch element SE1A has atransmission gate circuit inserted in a path for transmitting the signalfrom the input/output unit Pi to the circuit module Mi. Thistransmission gate circuit is configured by a p-type MOS transistor Q5and an n-type MOS transistor Q6 connected in parallel.

The switch element SE2A shown in FIG. 24 is a circuit for turning on/offthe signal Sin2 transmitted from the input/output unit Pi to the circuitmodule M(i+1) in the same way as the switch element SE2 shown in FIG. 22and is included in the switch circuit SWBi. The switch element SE2A hasa transmission gate circuit inserted in a path for transmitting thesignal from the input/output unit Pi to the circuit module M(i+1). Thistransmission gate circuit is configured by the p-type MOS transistor Q5and the n-type MOS transistor Q6 connected in parallel in the same wayas the switch element SE1A.

In the switch element SE1A, the control signal Sci is input to the gateof the p-type MOS transistor Q5, and the logically inverted controlsignal /Sci is input to the gate of the n-type MOS transistor Q6. On theother hand, in the switch element SE2A, the logically inverted controlsignal /Sci is input to the gate of the p-type MOS transistor Q5, andthe control signal Sci is input to the gate of the n-type MOS transistorQ6.

When the control signal Sci is at the low level (value “0”), the p-typeMOS transistor Q5 and the n-type MOS transistor Q6 of the switch elementSE1A are driven ON, and the switch element SE1A becomes the conductivestate. The signal SMin1 output from the input/output unit Pi is inputvia (through-hole) the switch element SE1A to the circuit module Mi.Further, the p-type MOS transistor Q5 and the n-type MOS transistor Q6of the switch element SE2A are driven OFF, the switch element SE2Abecomes cut off, and the circuit module M(i+1) and the input/output unitPi are disconnected. When the control signal Sci is at the high level(value “1”), the switch element SE2A becomes the conductive statereverse to that explained above. The signal SMin1 output from theinput/output unit Pi is input via (through-hole) the switch element SE2Ato the circuit module M(i+1). Further, the switch element SE1A becomescut off, and the circuit module Mi and the input/output unit Pi aredisconnected.

Note that, in the example of FIG. 24, in order to reduce the signaldelay due to the resistance component of the transmission gate circuit,the inverter circuits U5 and U6 are inserted in paths on the input side(input/output unit side) of the switch elements SE1A and SE2A.

FIG. 25 is a diagram showing a second example of the configuration ofthe switch elements for turning on/off a signal transmitted from acircuit module to an input/output unit.

A switch element SE3A shown in FIG. 25 is a circuit for turning on/offthe signal Sout1 transmitted from the circuit module Mi to theinput/output unit Pi in the same way as the switch element SE3 shown inFIG. 23 and is included in the switch circuit SWAi. The switch elementSE3A has a transmission gate circuit inserted in the path fortransmitting the signal from the circuit module Mi to the input/outputunit Pi. This transmission gate circuit is configured by a p-type MOStransistor Q5 and an n-type MOS transistor Q6 connected in parallel.

A switch element SE4A shown in FIG. 25 is a circuit for turning on/offthe signal Sout2 transmitted from the circuit module M(i+1) to theinput/output unit Pi in the same way as the switch element SE4 shown inFIG. 23 and is included in the switch circuit SWBi. The switch elementSE4A has a transmission gate circuit inserted in the path fortransmitting the signal from the circuit module M(i+1) to theinput/output unit Pi. This transmission gate circuit is configured by ap-type MOS transistor Q5 and an n-type MOS transistor Q6 connected inparallel in the same way as the switch element SE3A.

In the switch element SE3A, the control signal Sci is input to the gateof the p-type MOS transistor Q5, and the logically inverted controlsignal /Sci is input to the gate of the n-type MOS transistor Q6. On theother hand, in the switch element SE4A, the logically inverted controlsignal /Sci is input to the gate of the p-type MOS transistor Q5, andthe control signal Sci is input to the gate of the n-type MOS transistorQ6.

When the control signal Sci at the low level (value “0”), the p-type MOStransistor Q5 and the n-type MOS transistor Q6 of the switch elementSE3A are driven ON, and the switch element SE1A becomes the conductivestate. The signal Sout1 output from the circuit module Mi is input via(through-hole) the switch element SE3A to the input/output unit Pi.Further, the p-type MOS transistor Q5 and the n-type MOS transistor Q6of the switch element SE4A are driven OFF, the switch element SE4Abecomes cut off, and the circuit module M(i+1) and the input/output unitPi are disconnected. When the control signal Sci is at the high level(value “1”), the switch element SE4A becomes a conductive state reverseto that explained above. The signal Sout2 output from the circuit moduleM(i+1) is input to the input/output unit Pi via (through-hole) theswitch element SE4A. Further, the switch element SE3A becomes cut off,and the circuit module Mi and the input/output unit Pi are disconnected.

Note that in order to reduce the signal delay due to the resistancecomponent of the transmission gate circuit, the inverter circuits may beinserted in paths on the input side (circuit module side) of the switchelements SE1A and SE2A.

FIG. 26 is a diagram showing a third example of the configuration of theswitch elements for turning on/off a signal transmitted from aninput/output unit to a circuit module.

The switch elements SE1B and SE2B shown in FIG. 26 are obtained bydeleting the p-type MOS transistors Q5 of the switch elements SE1A andSE2A shown in FIG. 24. The basic operation is the same as that of theswitch elements SE1A and SE2A. Namely, when the control signal Sci is atthe low level (value “0”), the signal from the input/output unit Pi istransmitted to the circuit module Mi, and the input/output unit Pi andthe circuit module M(i+1) are disconnected. When the control signal Sciis at the high level (value “1”), the signal from the input/output unitPi is transmitted to the circuit module M(i+1), and the input/outputunit Pi and the circuit module Mi are disconnected.

FIG. 27 is a diagram showing a third example of the configuration of theswitch elements for turning on/off a signal transmitted from a circuitmodule to an input/output unit.

The switch elements SE3B and SE4B shown in FIG. 27 are obtained bydeleting the p-type MOS transistors Q5 of the switch elements SE3A andSE4A shown in FIG. 25. The basic operation is the same as that of theswitch elements SE3A and SE4A. Namely, when the control signal Sci is atthe low level (value “0”), the signal from the circuit module Mi istransmitted to the input/output unit Pi, and the input/output unit Piand the circuit module M(i+1) are disconnected. When the control signalSci is at the high level (value “1”), the signal from the circuit moduleM(i+1) is transmitted to the input/output unit Pi, and the input/outputunit Pi and the circuit module Mi are disconnected.

Note that when signals of a high level are input to the switch elementsshown in FIG. 26 and FIG. 27 (SE1B, SE2B, SE3B, SE4B), signals outputafter passing through these switch elements cause a voltage dropcorresponding to the threshold value of the n-type MOS transistor Q6.For this reason, where the switch elements shown in FIG. 26 and FIG. 27are used, it is required that the effect (delay, noise margin, etc.) bythis voltage drop upon the circuit operation be kept in a permissiblerange.

Here, the structure in a case where switch elements of the first exampleof the configuration (FIG. 22, FIG. 23) and the second example of theconfiguration (FIG. 24, FIG. 25) are formed on a semiconductor substratewill be explained with reference to FIGS. 28A and 28B and FIGS. 29A and29B.

FIGS. 28A and 28B are plan views showing an example of the structure ofthe switch elements (SE1 to SE4) of the first example of theconfiguration shown in FIG. 22 and FIG. 23. FIG. 28A shows an example ofa case where two MOS transistors each are formed in two active regions(D1, D2), and FIG. 28B shows an example of a case where one MOStransistor each is formed in the four active regions (D3 to D6).

In the structural example shown in FIG. 28A, the active regions D1 andD2 are formed aligned on the semiconductor substrate. An n-type impurityis introduced into the active region D1, and a p-type impurity isintroduced into the active region D2. The active regions D1 and D2 havefor example rectangular shapes as shown in FIG. 28A. The sizes arealmost the same. A region for electrically isolating elements indifferent active regions from each other (element isolation region) isprovided between the active regions.

On the active regions D1 and D2, gate electrodes G1 to G3 are providedvia (through-hole) a not shown gate oxidation mask.

The gate electrode G1 is provided over two active regions (D1, D2). In aportion facing the gate electrode G1 in the active region D1, a channelof the p-type MOS transistor Q1 is formed. Further, in the active regionD2, the channel of the n-type MOS transistor Q4 is formed in a portionfacing the gate electrode G1. The gate electrode G1 corresponds to theinput terminals Ti in the switch elements (SE1 to SE4) in the firstexample of the configuration.

The gate electrode G2 is provided on the active region D1 on the rightside of the gate electrode G1 in the figure. In the active region D1,the channel of the p-type MOS transistor Q2 is formed in a portionfacing the gate electrode G2. The gate electrode G3 is provided on theactive region D2 on the right side of the gate electrode G1 in thefigure. In the active region D2, the channel of the n-type MOStransistor Q3 is formed in a portion facing the gate electrode G3. Thegate electrodes G2 and G3 correspond to terminals for receiving as inputthe control signal Sci or the logically inverted signal /Sci thereof.

In the active region D1, a region A1 on the left side of the gateelectrode G1 corresponds to the source of the p-type MOS transistor Q1.This region A1 is connected via (through-hole) not shown vias(through-hole) to the metal interconnect W1. The metal interconnect W1corresponds to the power supply line VCC.

A region A2 sandwiched between the gate electrodes G1 and G2 in theactive region D1 corresponds to the drain of the p-type MOS transistorQ1 and the source of the p-type MOS transistor Q2. The drain of thep-type MOS transistor Q1 and the source of the p-type MOS transistor Q2are connected to each other in this region A2.

A region A3 on the right side of the gate electrode G2 in the activeregion D1 corresponds to the drain of the p-type MOS transistor Q2.Further, a region A4 on the right side of the gate electrode G3 in theactive region D2 corresponds to the drain of the n-type MOS transistorQ3. These regions A3 and A4 are connected via (through-hole) not shownvias (through-hole) and the metal interconnect W2 to each other.Connection points of the regions A3 and A4 correspond to the outputterminals To in the switch elements (SE1 to SE4) of the first example ofthe configuration.

In the active region D2, a region A5 sandwiched between the gateelectrodes G1 and G3 corresponds to the source of the n-type MOStransistor Q3 and the drain of the n-type MOS transistor Q4. The sourceof the n-type MOS transistor Q3 and the drain of the n-type MOStransistor Q4 are connected to each other in this region A5.

A region A6 on the left side of the gate electrode G1 in the activeregion D2 corresponds to the source of the n-type MOS transistor Q4.This region A6 is connected to the metal interconnect W3 via(through-hole) the not shown vias (through-hole). The metal interconnectW3 corresponds to the ground line VSS.

In the structural example shown in FIG. 28B, four active regions D3, D4,D5, and D6 are formed in a matrix on the semiconductor substrate. In theexample of FIG. 28B, the active region D4 is formed on the right side ofthe active region D3, the active region D6 is formed on the lower sideof the active region D3, and the active region D5 is formed on the lowerside of the active region D4 and the right side of the active region D6.n-type impurities are introduced into the active regions D3 and D4, andp-type impurities are introduced into the active regions D5 and D6. Theactive regions D3 to D6 have rectangular shapes for example as shown inFIG. 28B. The sizes are almost the same. The element isolation region isprovided between the active regions.

On the active regions D3 to D6, gate electrodes G4 to G6 are providedvia (through-hole) not shown gate oxidation masks.

The gate electrode G4 is provided over the active regions D3 and D6. Thechannel of the p-type MOS transistor Q1 is formed in a portion facingthe gate electrode G4 in the active region D3. Further, the channel ofthe n-type MOS transistor Q4 is formed in a portion facing the gateelectrode G4 in the active region D6. The gate electrode G4 correspondsto the input terminals Ti in the switch elements (SE1 to SE4) in thefirst example of the configuration.

The gate electrode G5 is provided on the active region D4. The channelof the p-type MOS transistor Q2 is formed in a portion facing the gateelectrode G5 in the active region D4. The gate electrode G6 is providedon the active region D5. The channel of the n-type MOS transistor Q3 isformed in a portion facing the gate electrode G6 in the active regionD5. The gate electrodes G5 and G6 correspond to terminals for receivingas input the control signal Sci or the logically inverted signal /Scithereof.

A region A7 on the left side of the gate electrode G4 in the activeregion D3 corresponds to the source of the p-type MOS transistor Q1.This region A7 is connected to the metal interconnect W4 via(through-hole) not shown vias (through-hole). The metal interconnect W4corresponds to the power supply line VCC.

A region A8 on the right side of the gate electrode G4 in the activeregion D3 corresponds to the drain of the p-type MOS transistor Q1.Further, a region A9 on the left side of the gate electrode G5 in theactive region D4 corresponds to the source of the p-type MOS transistorQ2. These regions A8 and A9 are connected to each other via(through-hole) not shown vias (through-hole) and metal interconnects W5W6, and W7.

A region A10 on the right side of the gate electrode G5 in the activeregion D4 corresponds to the drain of the p-type MOS transistor Q2.Further, a region A11 on the right side of the gate electrode G6 in theactive region D5 corresponds to the drain of the n-type MOS transistorQ3. These regions A3 and A4 are connected to each other via(through-hole) not shown vias (through-hole) and a metal interconnectW8. The connection points of the regions A10 and A11 correspond to theoutput terminals To in the switch elements (SE1 to SE4) in the firstexample of the configuration.

A region A12 on the left side of the gate electrode G6 in the activeregion D5 corresponds to the source of the n-type MOS transistor Q3.Further, a region A13 on the right side of the gate electrode G4 in theactive region D6 corresponds to the drain of the n-type MOS transistorQ1. These regions A12 and A13 are connected to each other via(through-hole) not shown vias (through-hole) and metal interconnects W9,W10, and W11.

A region A14 on the left side of the gate electrode G1 in the activeregion D6 corresponds to the source of the n-type MOS transistor Q4.This region A14 is connected to a metal interconnect W12 via(through-hole) not shown vias (through-hole). The metal interconnect W3corresponds to the ground line VSS.

FIGS. 29A and 29B are plan views showing an example of the structure ofswitch elements (SE1A to SE4A) in the second example of theconfiguration shown in FIG. 24 and FIG. 25. FIG. 29A shows an example ofa case where two MOS transistors each are formed in the two activeregions (D7, D8), and FIG. 29B shows an example of a case where one MOStransistor each is formed in the four active regions (D9 to D12).

In the structural example shown in FIG. 29A, the active regions D7 andD8 are formed aligned on the semiconductor substrate. An n-type impurityis introduced into the active region D7, and a p-type impurity isintroduced into the active region D8. The active regions D7 and D8 haverectangular shapes as shown in for example FIG. 29A. The sizes arealmost the same. An element isolation region is provided between theactive regions.

On the active regions D7 and D8, gate electrodes G7 to G9 are providedvia (through-hole) not shown gate oxidation masks.

The gate electrode G7 is provided over two active regions (D7, D8). Thechannel of the p-type MOS transistor Q7 is formed in a portion facingthe gate electrode G7 in the active region D7. Further, the channel ofthe n-type MOS transistor Q8 is formed in a portion facing the gateelectrode G7 in the active region D8.

Note that the p-type MOS transistor Q7 and the n-type MOS transistor Q8are transistors configuring the inverter circuit inserted in the path onthe input side of each of the switch elements (SE1A to SE4A). The gateelectrode G7 corresponds to the input terminal of this inverter circuit.

The gate electrode G8 is provided on the active region D7 on the rightside of the gate electrode G7 in the figure. The channel of the p-typeMOS transistor Q5 is formed in a portion facing the gate electrode G8 inthe active region D7. The gate electrode G9 is provided on the activeregion D8 on the right side of the gate electrode G7 in the figure, andthe channel of the n-type MOS transistor Q6 is formed in a portionfacing the gate electrode G9 in the active region D8. The gateelectrodes G8 and G9 correspond to the terminal for receiving as inputthe control signal Sci or the logically inverted signal /Sci thereof.

A region A15 on the left side of the gate electrode G7 in the activeregion D7 corresponds to the source of the p-type MOS transistor Q7.This region A15 is connected to a metal interconnect W13 via(through-hole) not shown vias (through-hole). The metal interconnect W13corresponds to the power supply line VCC.

A region A20 on the left side of the gate electrode G7 in the activeregion D8 corresponds to the source of the n-type MOS transistor Q8.This region A20 is connected to a metal interconnect W15 via(through-hole) not shown vias (through-hole). The metal interconnect W15corresponds to the power supply line VCC.

A region A16 sandwiched between the gate electrodes G7 and G8 in theactive region D7 corresponds to the drain of the p-type MOS transistorQ7 and the source of the p-type MOS transistor Q5. Further, a region A19sandwiched between the gate electrodes G7 and G8 in the active region D8corresponds to the drain of the n-type MOS transistor Q8 and the sourceof the n-type MOS transistor Q6. These regions A16 and A19 are connectedto each other via (through-hole) not shown vias (through-hole) and ametal interconnect W14. The connection points of the regions A16 and A19correspond to the output terminals of the inverter circuit explainedabove and, at the same time, correspond to the terminals on the sidesfor receiving as input the signal in the switch elements (SE1A to SE4A)in the second example of the configuration.

A region A17 on the right side of the gate electrode G8 in the activeregion D7 corresponds to the drain of the p-type MOS transistor Q5.Further, a region A18 on the right side of the gate electrode G9 in theactive region D8 corresponds to the drain of the n-type MOS transistorQ6. These regions A17 and A18 are connected to each other via(through-hole) not shown vias (through-hole) and a metal interconnectW16. The connection points of the regions A17 and A18 correspond to theterminals on the sides for outputting the signal in the switch elements(SE1A to SE4A) in the second example of the configuration.

In the structural example shown in FIG. 29B, four active regions D9,D10, D11, and D12 are formed in a matrix on the semiconductor substrate.In the example of FIG. 29B, the active region D11 is formed on the rightside of the active region D9, the active region D10 is formed on thelower side of the active region D9, and the active region D12 is formedon the lower side of the active region D11 and on the right side of theactive region D10. n-type impurities are introduced into the activeregions D9 and D11, and p-type impurities are introduced into the activeregions D10 and D12. The active regions D9 to D12 have rectangularshapes as shown in for example FIG. 29B. The sizes are almost the same.The element isolation region is provided between the active regions.

On the active regions D9 to D12, gate electrodes G10 to G12 are providedvia (through-hole) not shown gate oxidation masks.

The gate electrode G10 is provided over the active regions D9 and D10.The channel of the p-type MOS transistor Q7 is formed in a portionfacing the gate electrode G10 in the active region D9. The channel ofthe n-type MOS transistor Q8 is formed in a portion facing the gateelectrode G10 in the active region D10. The gate electrode G10corresponds to an input terminal of the inverter circuit configured by ap-type MOS transistor Q7 and an n-type MOS transistor Q8.

The gate electrode G11 is provided on the active region D11. The channelof the p-type MOS transistor Q5 is formed in a portion facing the gateelectrode G11 in the active region D11. The gate electrode G12 isprovided on the active region D12. The channel of the n-type MOStransistor Q6 is formed in a portion facing the gate electrode G12 inthe active region D12. The gate electrodes G11 and G12 correspond toterminals for receiving as input the control signal Sci or the logicallyinverted signal /Sci thereof.

A region A21 on the left side of the gate electrode G10 in the activeregion D9 corresponds to the source of the p-type MOS transistor Q7.This region A21 is connected to a metal interconnect W17 via(through-hole) not shown vias (through-hole). The metal interconnect W17corresponds to the power supply line VCC.

A region A28 on the left side of the gate electrode G10 in the activeregion D10 corresponds to the source of the n-type MOS transistor Q8.This region A28 is connected to a metal interconnect W19 via(through-hole) not shown vias (through-hole). The metal interconnect W19corresponds to the ground line VSS.

A region A22 on the right side of the gate electrode G10 in the activeregion D9 corresponds to the drain of the p-type MOS transistor Q7.Further, a region A27 on the right side of the gate electrode G10 in theactive region D10 corresponds to the drain of the n-type MOS transistorQ8. These regions A22 and A27 are connected to each other via(through-hole) not shown vias (through-hole) and a metal interconnectW18. The connection point of the regions A22 and A27 corresponds to theoutput terminal of the inverter circuit configured by a p-type MOStransistor Q7 and an n-type MOS transistor Q8.

A region A23 on the left side of the gate electrode G11 in the activeregion D11 corresponds to the source of the p-type MOS transistor Q5.Further, a region A26 on the left side of the gate electrode G12 in theactive region D12 corresponds to the source of the n-type MOS transistorQ6. These regions A23 and A26 are connected to each other via(through-hole) not shown vias (through-hole) and a metal interconnectW21. The connection points of the regions A23 and A26 correspond to theterminals for receiving as input the signals in the switch elements(SE1A to SE4A) in the second example of the configuration.

The metal interconnects W18 and W21 are connected via (through-hole) ametal interconnect W20. Due to this, output terminals of the invertercircuits (Q7, Q8) and input terminals of the switch elements (SE1A toSE4A) are connected.

A region A24 on the right side of the gate electrode G11 in the activeregion D11 corresponds to the drain of the p-type MOS transistor Q5.Further, a region A25 on the right side of the gate electrode G12 in theactive region D12 corresponds to the drain of the n-type MOS transistorQ6. These regions A24 and A25 are connected to each other via(through-hole) not shown vias (through-hole) and a metal interconnectW22. The connection points of the regions A24 and A25 correspond to theterminals on the sides for outputting the signals in the switch elements(SE1A to SE4A) in the second example of the configuration.

In the switch elements (SE1A to SE4A) of the second example of theconfiguration shown in FIG. 29A, a metal interconnect W14 and vias(through-hole) are provided in order to connect regions A16 and A19sandwiched between the gate electrode G7 and the gate electrodes G8 andG9. On the other hand, in the switch elements (SE1 to SE4) in the firstexample of the configuration shown in FIG. 28(A), it is not necessary toconnect regions A2 and A5 sandwiched between the gate electrode G1 andthe gate electrodes G2 and G3, therefore the metal interconnect and vias(through-hole) as shown in FIG. 29A are unnecessary. Accordingly, thearea of the switch elements (SE1 to SE4) of the first example of theconfiguration can be made smaller than that of the circuit obtained byadding inverter circuits (Q7, Q8) to the switch elements (SE1A to SE4A)of the second example of the configuration.

Note that when the transistors are formed in different active regions,as seen also by comparison of FIG. 28B and FIG. 29B, the areas of thetwo are not different so much. Further, when the inverter circuits (Q7,Q8) are deleted and only the switch elements (SE1A to SE4A) of thesecond example of the configuration are used, the area of the switchelements (SE1A to SE4A) of the second example of the configuration canbe made smaller than that of the switch elements (SE1 to SE4) of thefirst example of the configuration. However, in this case, a signaldelay occurs due to the resistance component of the transmission gatecircuits (Q5, Q6), therefore the operation speed of the circuit becomesslower in comparison with the case where the switch elements (SE1 toSE4) of the first example of the configuration are used.

Above, the switch elements included in the switch circuits SWAi and SWBiof the circuit module selection unit 50 were explained.

Next, a description will be given again with reference to FIG. 21. Thecontrol unit 60 generates control signals Sc1 to Sc32 for controllingthe operation of the circuit module selection unit 50 in response to thesignal stored in the storage unit 70 or the signal input from the signalinput unit 80.

The control unit 60 outputs the following control signals Sc1 to Sc32 inaccordance with the value of the integer n when the signal stored in thestorage unit 70 or the signal input from the signal input unit 80designates to disconnect the circuit module Mn (n indicates an integerfrom 1 to 33, same true below in the present embodiment) from allinput/output units.[2≦n≦32]

In this case, the control unit 60 sets the control signals Sc1 toSc(n−1) at the value “0” and sets the control signals Scn to Sc32 at thevalue “1”. Due to this, the switch circuits SWA1 to SWA(n−1) turn on,the switch circuits SWAn to SWA32 turn off, the switch circuits SWB1 toSWB(n−1) turn off, and the switch circuits SWBn to SWB32 are set ON. Asa result, the circuit modules M1 to M(n−1) are connected with theinput/output units P1 to P(n−1) in a one-to-one correspondence, thecircuit modules M(n+1) to M33 are connected with the input/output unitsPn to P32 in a one-to-one correspondence, and the circuit module Mn isdisconnected from all input/output units.[n=1]

In this case, the control unit 60 sets all of the control signals Sc1 toSc32 at the value “1”. Due to this, all of the switch circuits SWA1 toSWA32 are set OFF, and all of the switch circuits SWB1 to SWB32 are setON. As a result, the circuit modules M2 to M33 are connected with theinput/output units P1 to P32 in a one-to-one correspondence, and thecircuit module M1 is disconnected from all input/output units.[n=33]

In this case, the control unit 60 sets all of the control signals Sc1 toSc32 at the value “0”. Due to this, all of the switch circuits SWA1 toSWA32 are set ON, and all of the switch circuits SWB1 to SWB32 are setOFF. As a result, the circuit modules M1 to M32 are connected with theinput/output units P1 to P32 in a one-to-one correspondence, and thecircuit module. M33 is disconnected from all input/output units.

When the signal stored in the storage unit 70 has the predeterminedinitial value, the control unit 60 generates control signals Sc1 to Sc32in response to the signal input from the signal input unit 80, whilewhen the signal stored in the storage unit 70 has a value different fromthe above predetermined initial value, it generates control signals Sc1to Sc32 in response to the signal stored in the storage unit 70. Due tothis, in the initial state where for example no signals are written inthe storage unit 70 (case of inspection of the circuit modules etc.),the control signals Sc1 to Sc32 can be generated in response to thesignal input from the outside of the semiconductor integrated circuit tothe signal input unit 80, therefore the connections between theinput/output units and the circuit modules can be freely controlled.Further, after signals are written in the storage unit 70, the controlsignals Sc1 to SC32 can be generated in response to a written signal,therefore the connections between the input/output units and the circuitmodules can be fixed to the desired state without input of a signal fromthe outside.

The control unit 60, for example as shown in FIG. 21, has a decodingunit 601 and OR circuits 602-2 to 602-32.

The decoding unit 601 decodes a signal input from the storage unit 70 orthe signal input unit 80 and outputs the decoding result as the signalsSd1 to Sd32. Namely, when the signal input stored in the storage unit 70or the signal input from the signal input unit 80 designates todisconnect the circuit module Mn from all input/output units, thedecoding unit 601 generates the following signals Sd1 to Sd32 inaccordance with the value of the integer n. When “n” is an integer from1 to 32, only the signal Sdn is set at “1”. The other signals are set at“0”. When “n” is the integer 33, all of the signals Sd1 to Sd32 are setat the value “0”.

The signals Sd1 to Sd32 are signals for designating whether or not thecircuit modules M1 to M32 are disconnected from all input/output units,therefore in the following explanation, these will be called“designation signals Sd1 to Sd32”.

The decoding unit 601 generates designation signals Sd1 to Sd32 inresponse to a signal input from the signal input unit 80 when the signalstored in the storage unit 70 has the above predetermined initial valueand generates the designation signals Sd1 to Sd32 in response to asignal stored in the storage unit 70 where the signal stored in thestorage unit 70 has a value different from the above predeterminedinitial value.

Note that the designation signal Sd1 output by the decoding unit 601 inthe example of FIG. 21 is the same as the control signal Sci supplied tothe circuit module selection unit 50.

The OR circuits 602-2 to 602-32 are logical OR operation circuits eachhaving two inputs and one output and cascade connected in this order.The OR circuit 602-2 receives as input the designation signal Sd1(=control signal Sc1) at one of two inputs and receives as input thedesignation signal Sd2 at the other. The output of the OR circuit 602-2is supplied as the control signal Sc2 to the circuit module selectionunit 50. The OR circuit 602-k (k indicates an integer from 3 to 32, sametrue below in the present embodiment) receives as input the outputsignal of the OR circuit 602-(k−1) at one of two inputs and receives asinput a designation signal Sdk at the other. The output of the ORcircuit 602-k is supplied as a control signal Sck to the circuit moduleselection unit 50.

When a designation signal Sdj (j indicates an integer from 2 to 32, sametrue below in the present embodiment) of the decoding unit 601 becomesthe value “1”, the OR circuit 602-j to which this designation signal Sdjis input outputs a control signal Scj of “1”. When “j” is smaller than32, all of the control signals Sc(j+1) to Sc32 output from the ORcircuits 602-(j+1) to 602-32 after the OR circuit 602-j also become thevalue “1”. When the designation signal Sd1 (=control signal Sc1) of thedecoding unit 601 becomes the value “1”, the OR circuit 602-2 to whichthis designation signal Sd1 is input outputs the control signal Sc2having the value “1”. All of the control signals Sc3 to Sc32 output fromthe OR circuits 602-3 to 602-32 after this OR circuit 602-2 become thevalue “1”. On the other hand, when all designation signals (Sd1 to Sd32)of the decoding unit 601 become the value “0”, all of the input/outputsignals of the OR circuits 602-2 to 602-32 become the value “0”,therefore all of the control signals (Sc1 to Sc32) supplied to thecircuit module selection unit 50 become the value “0”.

Accordingly, when the circuit module Mn is disconnected from allinput/output units, when “n” is an integer from 2 to 32, the designationsignals Sd1 to Sd(n−1) are set at the value “0”, and the designationsignal Sdn is set at the value “1” by the decoding unit 601, thereforethe control signals Sc1 to Sc(n−1) become the value “0”, and the controlsignals Sc1 to Sc32 become the value “1”. When “n” is the integer 1, thedesignation signal Sd1 is set at the value “1” by the decoding unit 601,therefore all of the control signals Sc1 to Sc32 become the value “1”.When “n” is the integer 33, all of the designation signals Sd1 to Sd32are set at the value “0” by the decoding unit 601, therefore all of thecontrol signals Sc1 to Sc32 become the value “0”.

The storage unit 70 stores a signal for designating one circuit moduleto be disconnected from 32 input/output units (P1 to P32) among 33circuit modules (M1 to M33). Further, the storage unit 70 stores asignal having the predetermined initial value in the initial state whereno signal is written. The storage unit 70 can be configured by forexample a fuse element or nonvolatile memory.

The signal input unit 80 is a circuit for receiving as input a signaldesignating one circuit module to be disconnected from 32 input/outputunits (P1 to P32) and is used for receiving as input a signal to thecontrol unit 60 from the external device in for example a case ofinspecting a semiconductor integrated circuit.

The operation of fault repair in the semiconductor integrated circuitaccording to the present embodiment having the above configuration willbe explained with reference to FIG. 30 to FIG. 32.

FIG. 30 shows the default connection state before the inspection offaults. In the example shown in FIG. 30, the input/output units P101 toP108 and the circuit modules M101 to M108, the input/output units 201 toP208 and the circuit modules M201 to M208, the input/output units P301to P308 and the circuit modules M301 to M308, and the input/output unitsP401 to P408 and the circuit modules M401 to M408 are connected in aone-to-one correspondence. Further, the circuit module M501 isdisconnected from all input/output units and becomes the redundantcircuit module.

When explaining this default connection state by the notations shown inFIG. 21, the input/output units P1 to P24 and circuit modules M1 to M24and the input/output units P25 to P32 and circuit modules M26 to M33 areconnected in a one-to-one correspondence. Further, the circuit moduleM25 is disconnected from all input/output units and becomes theredundant circuit module. In this case, the control unit 60 sets thecontrol signals Sc1 to Sc24 at the value “0” and sets the controlsignals Sc25 to Sc32 at the value “1”. In the circuit module selectionunit 50, the switch circuits SWA1 to SWA24 turn on, the switch circuitsSWA25 to SWA32 turn off, the switch circuits SWB1 to SWB24 turn off, andthe switch circuits SWB25 to SWB32 turn on.

FIG. 31 shows the connection state in a case where the circuit moduleM204 has a fault. In this case, the connections between the input/outputunits and circuit modules shift from the circuit module M204 having thefault toward the redundant circuit module M501. Namely, the input/outputunits P204, P203, P202, P201, P301, P302, . . . , P307, and P308 areconnected with the circuit modules M203, M202, M201, M301, M302, . . . ,M307, M308, and M501 in a one-to-one correspondence, and the circuitmodule M204 is disconnected from all input/output units. The rest of theconnections is the same as that at the time of the default shown in FIG.30.

When explaining the connection state shown in FIG. 31 by notations shownin FIG. 21, the input/output units P1 to P12 and circuit modules M1 toM12 and the input/output units P13 to P33 and circuit modules M14 to M33are connected in a one-to-one correspondence, and the circuit module M13is disconnected from all input/output units. In this case, the controlunit 60 sets the control signals Sc1 to Sc12 at the value “0” and setsthe control signals Sc13 to Sc32 at the value “1”. In the circuit moduleselection unit 50, the switch circuits SWA1 to SWA12 turn on, the switchcircuits SWA13 to SWA32 turn off, the switch circuits SWB1 to SWB12 turnoff, and the switch circuits SWB13 to SWB32 turn on.

FIG. 32 shows the connection state in a case where the circuit moduleM404 has a fault. In this case, the connections of the input/outputunits and the circuit modules shift from the circuit module M404 havingthe fault toward the redundant circuit module M501. Namely, theinput/output units P404, P405, P406, P407, and P408 are connected withthe circuit modules M405, M406, M407, M408, and M501 in a one-to-onecorrespondence, and the circuit module M404 is disconnected from allinput/output units. The rest of the connections is the same as that atthe time of default shown in FIG. 30.

When explaining the connection state shown in FIG. 32 by the notationsshown in FIG. 21, the input/output units P1 to P29 and circuit modulesM1 to M29 and the input/output units P30 to P32 and circuit modules M31to M33 are connected in a one-to-one correspondence, and the circuitmodule M30 is disconnected from all input/output units. In this case,the control unit 60 sets the control signals Sc1 to Sc29 at the value“0” and sets the control signals Sc30 to Sc32 at the value “1”. In thecircuit module selection unit 50, the switch circuits SWA1 to SWA29 turnon, the switch circuits SWA30 to SWA32 turn off, the switch circuitsSWB1 to SWB29 turn off, and the switch circuits SWB30 to SWB32 turn on.

By the semiconductor integrated circuit according to the presentembodiment, 32 circuit modules are selected from among 33 circuitmodules (M1 to M33) in response to the signal input from the storageunit 70 or the signal input unit 80, and the selected 32 circuit modulesand 32 input/output units (P1 to P32) are connected in a one-to-onecorrespondence. To the input/output unit Pi, one circuit module selectedfrom two circuit modules (Mi, M(i+1)) is connected. Accordingly, itbecomes possible to design the layout so that the change of the signaldelay occurring where the connection between the input/output unit Piand the circuit modules (Mi, M(i+1)) is switched becomes smaller. Forexample, as shown in FIG. 19 and FIG. 21, by arranging the input/outputunits in numerical order (P1, P2, . . . , P32) and arranging the circuitmodules in numerical order (M1, M2, . . . , M33) along this layout, thedifference of distances between the input/output unit Pi and the circuitmodules (Mi, M(i+1)) is made smaller, and the signal change along withconnection switching can be made smaller.

10th Embodiment

Next, a 10th embodiment of the present invention will be explained.

The semiconductor integrated circuit according to the present embodimentis obtained by changing the control unit 60 (FIG. 21) in thesemiconductor integrated circuit according to the ninth embodimentexplained above. The rest of the configuration is the same as that ofthe semiconductor integrated circuit according to the ninth embodiment.

FIG. 33 is a diagram showing an example of the configuration of asemiconductor integrated circuit according to the present embodiment.The semiconductor integrated circuit shown in FIG. 33 is obtained byreplacing the control unit 60 in the semiconductor integrated circuitshown in FIG. 21 by a control unit 60A. The same notations in FIG. 21and FIG. 33 show same components.

In the example of FIG. 33, the control unit 60A has decoding units 6011and 6012, OR circuits 602-2 to 602-32, NOR circuits 603-1 to 603-32, andcontrol lines Lc1 to Lc8 and Lr1 to Lr4.

The control lines Lc1 to Lc8 are embodiments of the first control lineof the claims. The control lines Lr1 to Lr4 are embodiments of thesecond control line of the claims. The circuit including the decodingunits 6011 and 6012 is an embodiment of the first control unit of theclaims. The OR circuits 602-2 to 602-32 and the NOR circuits 603-1 to603-32 are embodiments of the second control unit of the claims.

The control lines Lc1 to Lc8 are formed extended in the verticaldirection in the figure, while the control lines Lr1 to Lr4 are formedextended in the lateral direction in FIG. 33.

In the example of FIG. 33, the control lines Lc1 to Lc8 and the controllines Lr1 to Lr4 schematically vertically cross. 32 cross points (CR1 toCR32) are formed by the crossing of the two. The cross points CR1, . . ., and CR8 are cross points of the control lines Lc1, . . . , and Lc8with the control line Lr1. The cross points CR9, . . . , and CR16 arecross points of the control lines Lc8, . . . , and Lc1 with the controlline Lr2. The cross points CR17, . . . , and CR24 are cross points ofthe control lines Lc1, . . . , and Lc8 with the control line Lr3. Thecross points CR25, . . . , and CR32 are cross points of the controllines Lc8, . . . , and Lc1 with the control line Lr4.

The decoding unit 6011 outputs a signal of the value “0” to one of thecontrol lines Lc1 to Lc8 or outputs the signal of the value “1” to allin response to a signal stored in the storage unit 70 or a signal inputfrom the signal input unit 80. In the same way, the decoding unit 6012outputs a signal of the value “0” to one of the control lines Lr1 to Lr4or outputs a signal of the value “1” to all in response to a signalstored in the storage unit 70 or a signal input from the signal inputunit 80. Accordingly, the circuit configured by the decoding units 6011and 6012 (first control circuit) selects one cross point from among the32 cross points (CR1 to CR32) in response to a signal stored in thestorage unit 70 or a signal input from the signal input unit 80 andoutputs a signal having the value “0” to two control lines forming theselected cross point or outputs a signal having the value “1” to allcontrol lines (Lc1 to Lc8 and Lr1 to Lr4) forming 32 cross points (CR1to CR32).

Further, when the signal stored in the storage unit 70 has apredetermined initial value, the decoding unit 6011 determines thesignal values of the control lines Lc1 to Lc8 in response to the signalinput from the signal input unit 80, while when the signal stored in thestorage unit 70 has a value different from the above predeterminedinitial value, it determines the signal values of the control lines Lc1to Lc8 in response to the signal stored in the storage unit 70. In thesame way, when the signal stored in the storage unit 70 has the abovepredetermined initial value, the decoding unit 6012 determines thesignal values of the control lines Lr1 to Lr4 in response to the signalinput from the signal input unit 80, while when the signal stored in thestorage unit 70 has a value different from the above predeterminedinitial value, it determines the signal values of the control lines Lr1to Lr4 in response to a signal stored in the storage unit 70. Namely,the circuit configured by the decoding units 6011 and 6012 (firstcontrol circuit) determines the signal values of the control lines inresponse to a signal input from the signal input unit 80 when the signalstored in the storage unit 70 has the above predetermined initial valueand determines signal values of the control lines in response to asignal stored in the storage unit 70 when the signal stored in thestorage unit 70 has a value different from the above predeterminedinitial value.

The NOR circuit 603-i (i indicates an integer from 1 to 32, same truebelow in the present embodiment.) operates the inverted OR logic of thesignals output to two control lines forming the cross point CRi, andoutputs the operation result as the signal Sdi. The signal Sdi outputfrom the NOR circuit 603-i corresponds to the designation signal Sdioutput from the decoding unit 601 to the OR circuit 602-i in the controlunit 60 (FIG. 21).

Next, the operation of the semiconductor integrated circuit shown inFIG. 33 will be explained.

When the cross point CRi is selected by the decoding units 6011 and6012, and the signal of the value “0” is output to the two control linesforming the selected cross point CRi, the designation signal Sdi outputfrom the NOR circuit 603-i becomes the value “1”. At this time, when “i”is an integer from 2 to 32, the control signal Sc1 output from the NORcircuit 603-1 and the control signals Sc2 to Sc(i−1) output from the ORcircuits 602-2 to 602-(i−1) become the value “0”, and the controlsignals Sci to Sc32 output from the OR circuits 602-i to 602-32 becomethe value “1”. Further, when “i” is the integer 1 at this time, thecontrol signal Sc1 output from the NOR circuit 603-1 and the controlsignals Sc2 to Sc32 output from the OR circuits 602-2 to 602-32 allbecome the value “1”. Accordingly, when the cross point CRi (i=1 to 32)is selected by the decoding units 6011 and 6012, the circuit module Miis selected as the circuit module disconnected from all input/outputunits. Then, the remaining 32 circuit modules and 32 input/output units(P1 to P32) are connected in a one-to-one correspondence.

On the other hand, when a signal of the value “1” is output to allcontrol lines forming the cross points CR1 to CR32 by the decoding units6011 and 6012, all of the designation signals Sd1 to Sd32 output fromthe NOR circuits 603-1 to 603-32 become the value “0”. When thedesignation signals Sd1 to Sd32 become the value “0”, all of theinput/output signals of the OR circuits 602-2 to 602-32 become the value“0”, therefore all of the control signals (Sc1 to Sc32) supplied to thecircuit module selection unit 50 become the value “0”. When all of thecontrol signals Sc1 to Sc32 become the value “0”, the circuit module M33is disconnected from all of the input/output units and the remaining 32circuit modules (M1 to M32) and 32 input/output units (P1 to P32) areconnected in a one-to-one correspondence.

By the semiconductor integrated circuit according to the presentembodiment, from among the 32 cross points (CR1 to CR32) formed by theeight control lines Lc1 to LC8 and four control lines Lr1 to LR4, onecross point CRi is selected by the decoding units 6011 and 6012. Then,by the setting of the two control lines forming this selected crosspoint CRi at the value “0”, the circuit module Mi corresponding to thecross point CRi is disconnected from all input/output units, and theremaining 32 circuit modules are connected with the 32 input/outputunits (P1 to P32) in a one-to-one correspondence. On the other hand,when all of the control lines forming the 32 cross points (CR1 to CR32)are set at the value “1”, the circuit module M33 is disconnected fromall input/output units and the remaining 32 circuit modules (M1 to M32)are connected with the 32 input/output units (P1 to P32) in a one-to-onecorrespondence. Namely, one circuit module is brought intocorrespondence with each of a plurality of cross points formed by aplurality of control lines (first control lines) and a plurality ofcontrol lines (second control lines). By giving the signal to eachcontrol line so that one cross point is selected from among theseplurality of cross points, the circuit module linked with this selectedcross point is disconnected and can be designated as the circuit modulefor disconnection. Accordingly, even when the number of circuit modulesable to be repaired is large, the circuit modules for disconnection canbe designated by a very small number of control lines in comparison withthe number of these circuit modules.

For example, in the semiconductor integrated circuit shown in FIG. 21,32 designation signals (Sd1 to Sd32) are generated at the decoding unit601 in order to indicate one circuit module as the disconnection targetfrom among 33 circuit modules (M1 to M33). Contrarily to this, in thesemiconductor integrated circuit shown in FIG. 33, it is possible toperform the same designation by 12 control lines (Lc1 to Lc8, Lr1 toLr4). Accordingly, the decoding units 6011 and 6012 of FIG. 33 can begiven a very simple configuration in comparison with the decoding unit601 of FIG. 21.

Note that, in the example of FIG. 33, the circuit modules are linkedwith all of the 32 cross points formed by the eight control lines (Lc1to Lc8) and four control lines (Lr1 to Lr4), but when the number offormed cross points is larger than the number of circuit modules, thecircuit modules may be linked with just part of the cross points.

Further, the input/output units, circuit modules, and cross points maybe freely laid out, but preferably the positional relationships of theabove are determined so that the distance between circuit modulesconnected to the same input/output unit becomes shorter and thedistances of the cross points linked with the circuit modules becomesshorter. For example, in the example shown in FIG. 33, the input/outputunits P1, . . . , and P32 and the circuit modules M1, M2, . . . , andM33 are arranged along a path obtained by connecting all cross pointsformed by the crossing of the control lines (Lc1 to Lc8, Lr1 to Lr4) ina line with the shortest distance. Then, the cross point located at thenearest position from each circuit module is linked with each circuitmodule. When employing this layout, for example, as shown in FIG. 33,the distance between the switch circuit (SWAi, SWBi) and the cross pointCRi can be made shorter. Due to this, the circuits generating thecontrol signals Sci in response to the signals of the control linesforming the cross point CRi (OR circuit 602-j, NOR circuit 603-i) can bearranged near the switch circuits (SWAi, SWBi) controlled by thesecontrol signals Sci. When this layout becomes close, it is not necessaryto lay a long interconnect in order to transmit the control signal Sci,therefore the interconnect resources can be saved.

11th Embodiment

Next, an 11th embodiment of the present invention will be explained.

The semiconductor integrated circuit according to the present embodimentis formed by providing a power supply switch unit 90 in thesemiconductor integrated circuit according to the above ninth embodiment(FIG. 19, FIG. 21). The rest of the configuration is the same as that ofthe semiconductor integrated circuit according to the ninth embodiment.

FIG. 34 is a diagram showing an example of the configuration of thesemiconductor integrated circuit according to the present embodiment.The semiconductor integrated circuit shown in FIG. 34 is obtained byadding the power supply switch unit 90 to the semiconductor integratedcircuit shown in FIG. 21. The same notations in FIG. 21 and FIG. 34 showthe same components.

The power supply switch unit 90 controls the supply of power to eachcircuit module (M1 to M33) in response to the signal output from thecontrol unit 60. Namely, it turns off the power supply of the circuitmodule disconnected from the input/output units P1 to P32.

The power supply switch unit 90, for example as shown in FIG. 34, haspower supply switch circuits PS1 to PS33.

The power supply switch circuit PSi (i indicates an integer from 1 to32, same true below in the present embodiment) is inserted in the powersupply line of the circuit module Mi, turns on when the designationsignal Sdi has the value “0”, and turns off where it has the value “1”.The designation signal Sdi becomes the value “1” when disconnecting thecircuit module Mi from all input/output units, therefore, in this case,the supply of the power to the circuit module Mi is cut off.

The power supply switch circuit PS33 is inserted in the power supplyline of the circuit module M33, turns on when the control signal /Sc32(the signal obtained by inverting the logic of the control signal Sc32)has the value “0”, while turns off when this signal has the value “1”.The control signal /Sc32 becomes the value “1” when disconnecting thecircuit module M33 from all input/output units, therefore, in this case,the supply of the power to the circuit module M33 is cut off.

FIG. 35A is a diagram showing an example of the configuration of thepower supply switch circuit PSi (i=1, . . . , 32). The power supplyswitch circuit PSi, for example as shown in FIG. 35A, has an n-type MOStransistor Qnh1, a p-type MOS transistor Qph1, and an inverter circuitU1.

The p-type MOS transistor Qph1 is connected at its source to the powersupply line VCC, connected at its drain to a virtual power supply lineV-VCC of the circuit module Mi, and receives as input the designationsignal Sdi at its gate. As the p-type MOS transistor Qph1, use may bemade of a p-type MOS transistor of a high threshold value type having asmaller leakage current in comparison with the usual p-type MOStransistor in the semiconductor integrated circuit.

The n-type MOS transistor Qnh1 is connected at its source to the groundline VSS and connected at its drain to a virtual ground line V-VSS ofthe circuit module Mi. As the n-type MOS transistor Qnh1, use may bemade of an n-type MOS transistor of a high threshold value type having asmaller leakage current in comparison with the usual n-type MOStransistor in the semiconductor integrated circuit.

The inverter circuit U1 inverts the logic of the signal input to thegate of the p-type MOS transistor Qph1 and inputs the same to the gateof the n-type MOS transistor Qnh1.

According to the power supply switch circuit PSi shown in FIG. 35A, whenthe designation signal Sdi has the value “0” (where the circuit moduleMi is connected to any input/output unit), a signal of the low level isinput to the gate of the p-type MOS transistor Qph1, a signal of thehigh level is input to the gate of the n-type MOS transistor Qnh1, andtherefore these transistors turn on. For this reason, power is suppliedto the circuit module Mi from the power supply line VCC and the powersupply line VSS. On the other hand, when the designation signal Sdi hasthe value “1” (where the circuit module Mi is disconnected from allinput/output units), both of the p-type MOS transistor Qph1 and then-type MOS transistor Qnh1 turn off, and the supply of the power to thecircuit module Mi is cut off.

FIG. 35B is a diagram showing an example of the configuration of thepower supply switch circuit PS33. The power supply switch circuit PS33has the same configuration as that of the power supply switch circuitPSi (i=1, . . . , 32) shown in FIG. 35A. The power supply switch circuitPS33 is different from the power supply switch circuit PSi shown in FIG.35A in the point that the control signal /Sc32 is input in place of thedesignation signal Sdi. The control signal /Sc 32 becomes the value “0”when any of the designation signals Sd1 to Sd32 becomes the value “1”.Namely, when any of the circuit modules M1 to M32 is disconnected fromthe input/output units, and the circuit module M33 is connected to theinput/output unit P32 in place of that, it becomes the value “0”. Inthis case, a signal of the low level is input to the gate of the p-typeMOS transistor Qph1, a signal of the high level is input to the gate ofthe n-type MOS transistor Qnh1, and both of these transistors turn on,therefore power is supplied to the circuit module M33 from the powersupply line VCC and the ground line VSS. On the other hand, the controlsignal /Sc32 becomes the value “1” when all of the designation signalsSd1 to Sd32 become the value “0”. Namely, this becomes the value “0”when the circuit modules M1 to M32 are connected to the input/outputunits, and the circuit module M33 is disconnected from the input/outputunit P32 as the redundant circuit module. In this case, both of thep-type MOS transistor Qph1 and the n-type MOS transistor Qnh1 turn off,and the supply of power to the circuit module Mi is cut off.

By the semiconductor integrated circuit according to the presentembodiment, a power supply switch circuit is inserted in the powersupply line to each circuit module. By controlling this, the supply ofpower to the circuit module disconnected from the input/output units iscut off, therefore wasted power consumption in circuit modules notcontributing to the operation of the circuit can be prevented, and thepower consumption can be reduced. When a fault causing a large currentto flow in the power supply line occurs in a circuit module, this is cutoff and the influence upon the power supply system and other circuitscan be prevented, therefore the drop of the yield due to a fault of acircuit module can be effectively suppressed.

12th Embodiment

Next, a 12th embodiment of the present invention will be explained.

FIG. 36 is a diagram showing an example of the configuration of asemiconductor integrated circuit according to the present embodiment.The semiconductor integrated circuit shown in FIG. 36 is obtained byreplacing the circuit module selection unit 50 in the semiconductorintegrated circuit shown in FIG. 19 by circuit module selection units 51and 52 and adding a circuit module M502 to this. The rest of theconfiguration is the same as that of the semiconductor integratedcircuit shown in FIG. 19. The same notations in FIG. 19 and FIG. 25 showsame components.

The circuit module selection unit 51 selects 16 circuit modules fromamong 17 circuit modules (M101, . . . , M108, M201, . . . , M208, M502)in response to a control signal supplied from a not shown control unitand connects the selected 16 circuit modules and 16 input/output units(P101, . . . , P108, P201, . . . , P208) in a one-to-one correspondence.The 17 circuit modules (M101, . . . , M108, M201, . . . , M208, M502)for switching of the circuit module selection unit 51 are a group ofcircuit modules which can replace each other's functions and form onecircuit module block.

Here, the circuit module selection unit 51 will be explained byreplacing the 17 circuit modules (M101, . . . , M108, M201, . . . ,M208, M502) and the 16 input/output units (P101, . . . , P108, P201, . .. , P208) by the following notations.

(Circuit Modules)

M101, . . . , M108→M1, . . . , M8

M208, . . . , M201→M10, . . . , M17

M502→M9

(Input/Output Units)

P101, . . . , P108→P1, . . . , P8

P208, . . . , P201→P9, . . . , P16

Explaining this by using above notations, the circuit module selectionunit 51 selects one of the circuit module Mi (i indicates an integerfrom 1 to 16, same true below in the present embodiment) or the circuitmodule M((i+1) in response to the control signal supplied from a notshown control unit and connects the selected circuit module to theinput/output unit Pi.

The circuit module selection unit 51 performing the switching operationcan be realized by the same configuration as that of for example thecircuit module selection unit 50 in FIG. 21. Namely, the circuit moduleselection unit 51 can be configured by decreasing the number ofinput/output units connected to the circuit module selection unit 50from 32 to 16 and decreasing the switch circuits in the inside matchingwith this. Further, the control unit for supplying the control signal tothe circuit module selection unit 51 can be realized by the sameconfiguration as that of for example the control unit 60 in FIG. 21.Namely, the number of the control signals output from the control unit60 may be decreased matching with the number of switch circuits of thecircuit module selection unit 51.

On the other hand, the circuit module selection unit 52 selects 16circuit modules from among 17 circuit modules (M301, . . . , M308, M401,. . . , M408, M501) in response to the control signal supplied from anot shown control unit and connects the selected 16 circuit modules with16 input/output units (P301, . . . , P308, P401, . . . , P408) in aone-to-one correspondence. The 17 circuit modules (M301, . . . , M308,M401, . . . , M408, M501) for switching of the circuit module selectionunit 52 are the group of circuit modules which can replace each other'sfunctions and form one circuit module block.

The circuit module selection unit 52 will be explained by replacingelements by notations as follows:

(Circuit modules)

M301, . . . , M308→M1, . . . , M8

M408, . . . , M401→M10, . . . , M17

M501→M9

(Input/Output Units)

P301, . . . , P308→P1, . . . , P8

P408, . . . , P401→P9, . . . , P16

When explaining this by using the above notations, the circuit moduleselection unit 52 selects one of the circuit module Mi or the circuitmodule M(i+1) in response to the control signal supplied from the notshown control unit and connects the selected circuit module to theinput/output unit Pi. This circuit module switching operation isequivalent to that of the previously explained circuit module selectionunit 51, therefore the circuit module selection unit 52 can be realizedby the same configuration as that of the circuit module selection unit51. Further, the control unit for supplying the control signal to thecircuit module selection unit 52 can be realized by the sameconfiguration as that of the control unit for supplying the controlsignal to the circuit module selection unit 51.

Next, the fault repair operation in the semiconductor integrated circuitaccording to the present embodiment having the above configuration willbe explained with reference to FIG. 37 and FIG. 38.

FIG. 37 shows the default connection state before inspection of thefaults. In the example shown in FIG. 37, the input/output units P101 toP108 and the circuit modules M101 to M108, the input/output units 201 toP208 and circuit modules M201 to M208, the input/output units P301 toP308 and circuit modules M301 to M308, and the input/output units P401to P408 and circuit modules M401 to M408 are connected in a one-to-onecorrespondence. Further, the circuit modules M501 and M502 aredisconnected from all input/output units.

FIG. 38 shows the connection state in a case where the circuit modulesM202 and M403 have faults. In this case, the circuit module M202 isdisconnected from all input/output units, and the destinations ofconnection of the input/output units P202, . . . , and P208 are switchedto the circuit modules M203, . . . , M208, and M502. Namely, theconnections between the input/output units and the circuit modules areshifted from the circuit module M202 having the fault toward the circuitmodule M502 unconnected at the time of the default. Further, in thiscase, the circuit modules M403 is disconnected from all input/outputunits, and the destinations of connection of the input/output unitsP403, . . . , and P408 are switched to the circuit modules M404, . . . ,M408, and M501. Namely, the connections between the input/output unitsand the circuit modules shift from the circuit module M403 having thefault toward the circuit module M501 unconnected at the time of thedefault. The rest of the connections are the same as that at the time ofthe default shown in FIG. 37.

The semiconductor integrated circuit according to the present embodimenthas two circuit module blocks each being configured by a plurality ofcircuit modules which can replace each other's functions. Each of thesetwo circuit modules includes one redundant circuit module and can repairone faulty circuit module for each circuit module block. Accordingly, inthe overall circuit, as shown in FIG. 38, two faulty circuit modules canbe repaired, and the number of the circuit modules which can be repairedcan be increased in comparison with the semiconductor integrated circuitshown in FIG. 19 having only one circuit module block.

13th Embodiment

Next, a 13th embodiment of the present invention will be explained.

In the semiconductor integrated circuit shown (in FIG. 21, it ispossible to designate circuit modules to be disconnected frominput/output units one by one and switch the connections thereof, butwhen the number of circuit modules becomes large, it is necessary togenerate control signals in proportion to that number, therefore thescale of the control circuit becomes large. In the semiconductorintegrated circuit according to the present embodiment, by disconnectinga plurality of circuit modules from input/output units all together andswitching the connections thereof all together, the control circuit issimplified.

FIG. 39 is a diagram showing an example of the configuration of thesemiconductor integrated circuit according to a 13th embodiment of thepresent invention. The semiconductor integrated circuit shown in FIG. 39is obtained by replacing the circuit module selection unit 50 in thesemiconductor integrated circuit shown in FIG. 19 by circuit moduleselection units 51, 52, 53, and 54 and replacing the circuit module M501by the circuit modules M109, M209, M309, and M409. The rest of theconfiguration is the same as that of the semiconductor integratedcircuit shown in FIG. 19. The same notations in FIG. 19 and FIG. 39 showthe same components.

The circuit module selection unit 51 selects eight circuit modules fromamong nine circuit modules (M101, . . . , M109) in response to controlsignals Sc1 to Sc9 supplied from the control unit 60B (FIG. 40)explained later and connects the selected eight circuit modules andeight input/output units (P101, . . . , P108) in a one-to-onecorrespondence. Namely, the circuit module selection unit 51 selects oneof the circuit module M(100+i) or circuit module M(100+i+1) in responseto the control signal Sci (i indicates an integer from 1 to 8, same truebelow in the present embodiment) and connects the selected circuitmodule to the input/output unit P(100+i).

The circuit module selection unit 52 selects eight circuit modules fromamong nine circuit modules (M201, . . . , M209) in response to thecontrol signals Sc1 to Sc9 and connects the selected eight circuitmodules and eight input/output units (P201, . . . , P208) in aone-to-one correspondence. Namely, the circuit module selection unit 52selects one of the circuit module M(200+i) or circuit module M(200+i+1)in response to the control signal Sci and connects the selected circuitmodule to the input/output unit P(200+i).

The circuit module selection unit 53 selects eight circuit modules fromamong nine circuit modules (M301, . . . , M309) in response to thecontrol signals Sc1 to Sc9 and connects the selected eight circuitmodules and eight input/output units (P301, . . . , P308) in aone-to-one correspondence. Namely, the circuit module selection unit 53selects one of the circuit module M(300+i) or circuit module M(300+i+1)in response to the control signal Sci and connects the selected circuitmodule to the input/output unit P(300+i).

The circuit module selection unit 54 selects eight circuit modules fromamong nine circuit modules (M401, . . . , M409) in response to thecontrol signals Sc1 to Sc9 and connects the selected eight circuitmodules and eight input/output units (P401, . . . , P408) in aone-to-one correspondence. Namely, the circuit module selection unit 54selects one of the circuit module M(400+i) or circuit module M(400+i+1)in response to the control signal Sci and connects the selected circuitmodule to the input/output unit P(400+i).

FIG. 40 is a diagram showing an example of the configuration of aprincipal portion of the semiconductor integrated circuit shown in FIG.39. The semiconductor integrated circuit according to the presentembodiment, for example as shown in FIG. 39, has a control unit 60B, astorage unit 70B, a signal input unit 80B, and a power supply switchunit 90B. Further, in the example of configuration of FIG. 39, thecircuit module selection unit 51 has switch circuits SWA101 to SWA108and SWB101 to SWB108. The circuit module selection unit 52 has switchcircuits SWA201 to SWA208 and SWB201 to SWB208. The circuit moduleselection unit 53 has switch circuits SWA301 to SWA308 and SWB301 toSWB308. The circuit module selection unit 54 has switch circuits SWA401to SWA408 and SWB401 to SWB408.

The switch circuit SWA(100+i) is connected between the input/output unitP(100+i) and the circuit module M(100+i), turns on when the controlsignal Sci has the value “0”, and turns off when it has the value “1”.The switch circuit SWB(100+i) is connected between the input/output unit(100+i) and the circuit module M(100+i+1), turns off when the controlsignal Sci has the value “0”, and turns on when it has the value “1”.The switch circuit SWA(200+i) is connected between the input/output unitP(200+i) and the circuit module M(200+i), turns on when the controlsignal Sci has the value “0”, and turns off when it has the value “1”.The switch circuit SWB(200+i) is connected between the input/output unit(200+i) and the circuit module M(200+i+1), turns off when the controlsignal Sci has the value “0”, and turns on when it has the value “1”.The switch circuit SWA(300+i) is connected between the input/output unitP(300+i) and the circuit module M(300+i), turns on when the controlsignal Sci has the value “0”, and turns off when it has the value “1”.The switch circuit SWB(300+i) is connected between the input/output unit(300+i) and the circuit module M(300+i+1), turns off when the controlsignal Sci has the value “0”, and turns on when it has the value “1”.The switch circuit SWA(400+i) is connected between the input/output unitP(400+i) and the circuit module M(400+i), turns on when the controlsignal Sci has the value “0”, and turns off when it has the value “1”.The switch circuit SWB(400+i) is connected between the input/output unit(400+i) and the circuit module M(400+i+1), turns off when the controlsignal Sci has the value “0”, and turns on when it has the value “1”.

The control unit 60B generates control signals Sc1 to Sc9 for commonlycontrolling the circuit module selection units 51 to 54 in response to asignal stored in the storage unit 70B or a signal input from the signalinput unit 80B.

A set of four circuit modules {M(100+n), M(200+n), M(300+n), M(400+n)}(n indicates an integer from 1 to 9, same true below in the presentembodiment) arranged aligned in the vertical direction in FIG. 39 andFIG. 40 will be called the n-th circuit module set. When the signalstored in the storage unit 70B or the signal input from the signal inputunit 80B designates to disconnect the above n-th circuit module set fromall input/output units, the control unit 60B outputs the followingcontrol signals Sc1 to Sc9 in accordance with the value of the integern.[2≦n≦8]

In this case, the control unit 60B sets the control signals Sc1 toSc(n−1) at the value “0” and sets the control signals Sc1 to Sc8 at thevalue “1”. Due to this, the switch circuits SWA(100+n), SWA(200+n),SWA(300+n), and also SWA(400+n) turn off, the switch circuitsSWB(100+n−1), SWB(200+n−1), SWB(300+n−1), and SWB(400+n−1) turn off, andtherefore the four circuit modules belonging to the n-th circuit moduleset are disconnected from all input/output units. Further, when “p” isan integer from 1 to (n−1), the switch circuits SWA(100+p), SWA(200+p),SWA(300+p), and SWA(400+p) turn on, and the switch circuits SWB(100+p),SWB(200+p), SWB(300+p), and SWA(400+p) turn off. For this reason, thefour circuit modules belonging to the p-th circuit module set areconnected to the four input/output units P(100+p), P(200+p), P(300+p),and P(400+p). Further, when “q” is an integer from n to 8, the switchcircuits SWA(100+q), SWA(200+q), SWA(300+q), and SWA(400+q) turn off,and the switch circuits SWB(100+q), SWB(200+q), SWB(300+q), andSWA(400+q) turn on. For this reason, the four circuit modules belongingto the (q+1)th circuit module set are connected to the four input/outputunits P(100+q), P(200+q), P(300+q), and P(400+q).

[n=1]

In this case, the control unit 60B sets all of the control signals Sc1to Sc8 at the value “1”. Due to this, all of the switch circuits SWA101,SWA201, SWA301, and SWA401 turn off, therefore the first circuit moduleset is disconnected from all input/output units. Further, when “i” is aninteger from 1 to 8, the switch circuits SWA(100+i), SWA(200i),SWA(300+i), and SWA(400+i) turn off, and the switch circuits SWB(100+i),SWB(200+i), SWB(300+i), and SWA(400+i) turn on. For this reason, fourcircuit modules belonging to the (i+1)th circuit module set areconnected to four input/output units P(100+i), P(200+i), P(300+i), andP(400+i).[n=9]

In this case, the control unit 60B sets all of the control signals Sc1to Sc8 at the value “0”. Due to this, all of the switch circuits SWB108,SWB208, SWB308, and SWB408 turn off” therefore the fifth circuit moduleset is disconnected from all input/output units. Further, when “i” is aninteger from 1 to 8, the switch circuits SWA(100+i), SWA(200i),SWA(300+i), and SWA(400+i) turn on, and the switch circuits SWB(100+i),SWB(200+i), SWB(300+i), and SWA(400+i) turn off. For this reason, fourcircuit modules belonging to the i-th circuit module set are connectedto four input/output units P(100+i), P(200+i), P(300+i), and P(400+i).

Further, the control unit 60B generates control signals Sc1 to Sc8 inresponse to a signal input from the signal input unit 80B when thesignal stored in the storage unit 70B has the predetermined initialvalue and generates the control signals Sc1 to Sc8 in response to asignal stored in the storage unit 70B when the signal stored in thestorage unit 70B has a value different from the above predeterminedinitial value. Due to this, in for example the initial state where nosignal has been written in the storage unit 70B (case where theinspection of circuit modules is carried out etc.), the control signalsSc1 to Sc8 can be generated in response to a signal input to the signalinput unit 80B from the outside of the semiconductor integrated circuit,therefore the connection between input/output units and circuit modulescan be freely controlled. Further, after a signal is written in thestorage unit 70B, the control signals Sc1 to Sc8 can be generated inresponse to the written signal, therefore the connection betweeninput/output units and circuit modules can be fixed to a desired statewithout receiving as input a signal from the outside.

The control unit 60B, for example as shown in FIG. 40, has a decodingunit 601B and OR circuits 602-2 to 602-8.

The decoding unit 601B decodes the signal input from the storage unit70B or the signal input unit 80B and outputs the decoding result asdesignation signals Sd1 to Sd8. Namely, when it is indicated in thesignal stored in the storage unit 70B or the signal input from thesignal input unit 80B so as to disconnect the n-th circuit module setfrom all input/output units, the decoding unit 601B generates thefollowing designation signals Sd1 to Sd8 in accordance with the value ofthe integer n. When “n” is an integer from 1 to 8, only the designationsignal Sdn is set at the value “1”, and the other designation signalsare set at the value “0”. When “n” is the integer 9, all of thedesignation signals Sd1 to Sd8 are set at the value “0”.

Further, the decoding unit 601B generates designation signals Sd1 to Sd8in response to a signal input from the signal input unit 80B when thesignal stored in the storage unit 70B has the above predeterminedinitial value and generates designation signals Sd1 to Sd8 in responseto the signal stored in the storage unit 70B when the signal stored inthe storage unit 70B has a value different from the above predeterminedinitial value.

Note that, in the example of FIG. 40, the designation signal Sd1 outputby the decoding unit 601B is the same as the control signal Sc1 suppliedto the circuit module selection units 51 to 54. The OR circuits 602-2 to602-8 are logical OR operation circuits each having two inputs and oneoutput and cascade connected in this order. The OR circuit 602-2receives as input the designation signal Sd1 (=control signal Sc1) atone of two inputs and receives as input the designation signal Sd2 atthe other input. The output of the OR circuit 602-2 is supplied as thecontrol signal Sc2 to the circuit module selection units 51 to 54. TheOR circuit 602-k (k indicates an integer from 3 to 8, same true below inthe present embodiment) receives as input the output signal of the ORcircuit 602-(k−1) at one of two inputs and receives as input thedesignation signal Sdk at the other. The output of the OR circuit 602-kis supplied as the control signal Sck to the circuit module selectionunits 51 to 54.

When the designation signal Sdj (j indicates an integer from 2 to 8,same true below in the present embodiment) of the decoding unit 601Bbecomes the value “1”, the OR circuit 602-j to which this designationsignal Sdj is input outputs the control signal Scj having the value “1”.When “j” is smaller than 8, control signals Sc(j+1) to Sc8 output fromthe OR circuits 602-(j+1) to 602-8 after the OR circuit 602-j become thevalue “1”. When the designation signal Sd1 (=control signal Sc1) of thedecoding unit 601B becomes the value “1”, the OR circuit 602-2 to whichthis designation signal Sd1 is input outputs the control signal Sc2having the value “1”. The control signals Sc3 to Sc32 output from the ORcircuits 602-3 to 602-8 after the OR circuit 602-2 become the value “1”.On the other hand, when all designation signals (Sd1 to Sd8) of thedecoding unit 601B become the value “0”, all of input/output signals ofthe OR circuits 602-2 to 602-8 become the value “0”, therefore controlsignals (Sc1 to Sc8) supplied to the circuit module selection unit 50become the value “0”.

Accordingly, in the case where the n-th circuit module set isdisconnected from all input/output units, when “n” is an integer from 2to 8, the designation signals Sd1 to Sd (n−1) are set at the value “0”and the designation signal Sdn is set at the value “1” by the decodingunit 601B, therefore the control signals Sc1 to Sc(n−1) become the value“0”, and the control signals Scn to Sc8 become the value “1”. When “n”is the integer 1, the designation signal Sd1 is set at the value “1” bythe decoding unit 601B, therefore all of the control signals Sc1 to Sc8become the value “1”. When “n” is the integer 8, all of the designationsignals Sd1 to Sd8 are set at the value “0” by the decoding unit 601B,therefore all of the control signals Sc1 to Sc8 become the value “0”.

The storage unit 70B stores a signal designating one circuit module setto be disconnected from all input/output units among nine circuit modulesets (the first circuit module set to the ninth circuit module set).Further, the storage unit 70B stores a signal having a predeterminedinitial value in the initial state where no signal is written. Thestorage unit 70B can be configured by for example a fuse element ornonvolatile memory.

The signal input unit 80B is a circuit for receiving as input a signaldesignating one circuit module set to be disconnected from allinput/output units and is used for receiving as input a signal to thecontrol unit 60B from an outside device in for example the case ofinspecting a semiconductor integrated circuit.

The power supply switch unit 90B controls the supply of power to thecircuit module sets (the first circuit module set to the ninth circuitmodule set) in response to the signal output from the control unit 60B.Namely, it turns off the power source of the circuit module setdisconnected from the input/output units.

The power supply switch unit 90B, for example as shown in FIG. 40, haspower supply switch circuits PS101 to PS109.

The power supply switch circuit PS(100+i) (i=1, . . . , 8) is insertedin the power supply line of the i-th circuit module set. It turns onwhen the designation signal Sdi has the value “0” and turns off when ithas the value “1”. The power supply switch circuit PS(100+i) has acircuit configuration the same as for example the power supply switchcircuit PSi shown in FIG. 35A.

The power supply switch circuit PS109 is inserted in the power supplyline of the ninth circuit module set, turns on when the control signalSc8 has the value “1”, and turns off when it has the value “0”. Thepower supply switch circuit PS109 has a circuit configuration the sameas for example the power supply switch circuit PS33 shown in FIG. 35B.

A fault repair operation in a semiconductor integrated circuit accordingto the present embodiment having the above configuration will beexplained with reference to FIG. 41 and FIG. 42.

FIG. 41 shows a default connection state before the inspection forfaults. In the example shown in FIG. 41, the input/output units P101 toP108 and circuit modules M101 to M108, the input/output units P201 toP208 and circuit modules M201 to M208, the input/output units P301 toP308 and circuit modules M301 to M308, and the input/output units P401to P408 and circuit modules M401 to M408 are connected in a one-to-onecorrespondence. Further, the circuit modules M109, M209, M309, and M409are disconnected from all input/output units. In other words, the firstcircuit module set to the eight circuit module set are connected to theinput/output units, and the ninth circuit module set becomes redundant.

FIG. 42 shows the connection state in the case where the circuit moduleM204 has a fault. In this case, the fourth circuit module set {M104,M204, M304, M404} including the circuit module M204 is disconnected fromthe input/output units. Further, the destinations of connection of theinput/output units P104, . . . , and P108 are switched to the circuitmodules M105, . . . , and M109, the destinations of connection of theinput/output units P204, . . . , and P208 are switched to the circuitmodules M205, . . . , and M209, the destinations of connection of theinput/output units P304, . . . , and P308 are switched to the circuitmodules M305, . . . , and M309, and the destinations of connection ofthe input/output units P404, . . . , and P408 are switched to thecircuit modules M405, . . . , and M409. Namely, the connections betweenthe input/output units and circuit module sets wholly shift from thefourth circuit module set including the fault toward the ninth circuitmodule set unconnected at the time of the default. The rest of theconnections is the same as that at the time of the default shown in FIG.41.

By the semiconductor integrated circuit according to the presentembodiment, by the same control signal supplied from the control unit60B, the connection states of all circuit modules belonging to the samecircuit module set are commonly controlled. Due to this, the number ofcontrol signals can be greatly decreased in comparison with the casewhere the connection states with input/output units are independentlycontrolled for individual circuit modules, therefore the circuitconfiguration of the control unit 60B can be simplified.

Further, the power sources of all circuit modules belonging to the samecircuit module set are commonly controlled, therefore the number of thepower supply switch circuits can be decreased in comparison with thecase where power sources of individual circuit modules are controlled.

Further, when inspecting for faults, the presence of faults may beinspected for each circuit module set, therefore the inspection time canbe shortened in comparison with the case of inspecting individualcircuit modules.

Further, when information of a faulty circuit module is written into afuse or other storage element forming the storage unit 70B, theinformation of the presence of faults may be written for each circuitmodule set, therefore the amount of information becomes smaller, and thetime required for the write processing can be shortened.

14th Embodiment

Next, a 14 embodiment of the present invention will be explained. Thepresent embodiment relates to a method of production of a semiconductorintegrated circuit.

FIG. 43 is a flow chart showing an example of the method of productionof the semiconductor integrated circuit shown in FIG. 21.

Step ST401

A circuit shown in FIG. 21 is formed on a semiconductor substrate.

Step ST402

For example, an outside inspection system generates a signal designatingthe circuit modules to be disconnected from all input/output units (P1to p32) and inputs it to the signal input unit 80. The write processinghas not yet been carried out for the storage unit 70 formed at stepST401 at this time, therefore a signal having a predetermined initialvalue is stored. Accordingly, the control unit 60 generates the controlsignals Sc1 to Sc32 so as to disconnect the circuit modules designatedby the signal input to the signal input unit 80 from all input/outputunits.

Step ST403

By a scan path test or other inspection technique, the operations of thecircuit modules connected to the input/output units at present areinspected.

Step ST404

It is judged whether or not the inspection of step ST403 detects acircuit module having a fault.

Steps ST405, ST406, and ST407

When it is judged at step ST404 that a circuit module having a fault isdetected and then two or more faulty circuit modules in total includingthis faulty circuit module are detected, the semiconductor integratedcircuit being inspected is judged defective and the processing ends(step ST407). On the other hand, when there is still only one detectedfaulty circuit module, a signal designating the detected faulty circuitmodule as the circuit module to be disconnected from all input/outputunits is supplied to the signal input unit 80 by the inspection systemetc. (step ST406), and the inspection of step ST403 is carried outagain.

Step ST408

When circuit module having a fault is not detected at step ST404, asignal designating any faulty circuit module to be disconnected from allinput/output units is determined in response to the signal input to thesignal input unit 80 at this time and written into the storage unit 70.For example, when the storage unit 70 is configured by a fuse, theprocessing of disconnecting the fuse is carried out. When the signaldifferent from the initial value is written into the storage unit 70,the control unit 60 generates control signals Sc1 to Sc32 in response tothe signal stored in this storage unit 70. Due to this, the circuitmodule judged as faulty in the inspection of step ST403 is disconnectedfrom all input/output units.

An explanation was given above of several embodiments of the presentinvention, but the present invention is not limited to only the aboveembodiments and includes various modifications as well for example aswill be explained next.

In the semiconductor integrated circuit shown in FIGS. 1A and 1B, thenumber of circuit modules which can be selectively connected withrespect to one input/output unit was made two, but this number may bechanged. For example, input/output units selecting and connecting one oftwo circuit modules and input/output units selecting and connecting oneof three circuit modules may be mixed. The configurations of the circuitmodule selection units in the above embodiments are just examples. Thepresent invention is not limited to them. For example, the number ofinput/output units provided in the general circuit block is set at R,and the number of circuit modules is set at N. In this case, the circuitmodule selection unit has at least 2×R switch circuits. Each of theseswitch circuits is connected between one circuit module and oneinput/output unit. Each of R number of input/output units is connectedvia (through-hole) a plurality of switch circuits to a plurality ofcircuit modules. At least a portion of the N number of circuit modulesare connected to a plurality of input/output units via (through-hole) aplurality of switch circuits. One of the plurality of switch circuitsconnected to the same input/output unit turns on in response to acontrol signal supplied from the control unit. One of a plurality ofswitch circuits connected to the same circuit module turns on or turnsoff or all turn off in response to a control signal supplied from thecontrol unit. By configuring the circuit module selection unit in thisway, it is possible to select R number of circuit modules from among Nnumber of circuit modules in response to the control signal and connectthese with R number of input/output units in a one-to-onecorrespondence.

The circuit module selection unit in the present invention may connectthe signal input terminal of the circuit module disconnected from allinput/output units to an interconnect having a predetermined potential.In the switch elements shown in FIGS. 22, 24, and 26, the outputterminals To become the high impedance state at the time of OFF. Forthis reason, when the circuit module is disconnected-from allinput/output units, the signal input terminal of that circuit modulebecomes the high impedance state, and the potential becomes unstable.When power is supplied to the circuit module in this state, the circuitinside the circuit module operates in accordance with the unstablepotential of the signal input terminal, therefore wasted power isconsumed due to a penetration current or the like. Therefore, if thesignal input terminal of the circuit module disconnected from allinput/output units is connected to an interconnect having tapredetermined potential as described above, the potential of the signalinput terminal can be stabilized, therefore the increase of the powerconsumption due to the penetration current can be prevented.

FIG. 44 is a diagram showing an example of the configuration in a casewhere switch circuits SWC1 to SWC33 are provided in the circuit moduleselection unit 50 in the semiconductor integrated circuit shown in FIG.21. The switch circuits SWC1 to SWC33 are circuits for connecting thesignal input terminals of the circuit modules M1 to M33 to theinterconnect having the predetermined potential. The switch circuitsSWC1 to SWC33 are connected between signal input terminals of thecircuit modules M1 to M33 and the ground line VSS. The switch circuitSWCi (i=1, . . . , 32) turns on when the designation signal Sdi has thevalue “1”, that is, where the circuit module Mi is disconnected from allinput/output units, and turns off in other cases. The switch circuitSWC33 turns on when the control signal Sc32 is “0”, that is when thecircuit module M33 is disconnected from all input/output units, andturns off in other cases.

In the semiconductor integrated circuit shown in FIG. 39, the number ofcircuit modules included in each of eight circuit module sets is madefour, but any number made be used in the present invention. Namely, whenthere are a plurality of circuit module sets, the numbers of circuitmodules included in each of them may be different.

All of the semiconductor integrated circuits explained above may beformed on the same semiconductor chip. For example, a system-in-package(SIP) or other technique may be used to form a plurality ofsemiconductor chips.

In the embodiments explained above, a CMOS type semiconductor integratedcircuit was mainly explained as an example, but the present invention isnot limited to this. The present invention can be applied to integratedcircuits configured by various circuit elements such as bipolartransistors.

The numerical values specifically shown in the above embodiments (numberof circuit modules, number of input/output units, number of circuitmodule blocks, etc.) are just examples and can be appropriately changed.

It should be understood by those skilled in the art that variousmodifications, combinations, sub-combinations and alterations may occurdepending on design requirements and other factors insofar as they arewithin the scope of the appended claims or the equivalents thereof.

1. A semiconductor integrated circuit comprising; N (N indicates aninteger of N≧2) number of circuit modules which can replace each other'sfunctions; circuit blocks each having R (R indicates an integer of1≦R<N) number of input/output units for outputting at least one signalto one circuit module and receiving as input at least one signalgenerated in that one circuit module; and a circuit module selectionunit configured to select R number of circuit modules from among the Nnumber of circuit modules in response to a control signal, connect theselected R number of circuit modules and R number of input/output unitsof the circuit block in a one-to-one, correspondence, and connect onecircuit module selected in response to the control signal from at leasttwo circuit modules to each of the R number of input/output units.
 2. Asemiconductor integrated circuit as set forth in claim 1, wherein thecircuit comprise a control unit configured to generate the controlsignal of the circuit module selection unit so that a faulty circuitmodule among the N number of circuit modules is disconnected from the Rnumber of input/output units.
 3. A semiconductor integrated circuit asset forth in claim 2, wherein the circuit has a storage unit for storinga signal designating (N−R) number of circuit modules which should bedisconnected from the R number of input/output units, and the controlunit generates a control signal in accordance with the signal stored inthe storage unit.
 4. A semiconductor integrated circuit as set forth inclaim 2, wherein the circuit comprise a signal input unit for receivingas input a signal designating (N−R) number of circuit modules whichshould be disconnected from the R number of input/output units, and thecontrol unit is configured to generate the control signal in accordancewith the signal input to the signal input unit.
 5. A semiconductorintegrated circuit as set forth in claim 1, wherein the circuitcomprises; a storage unit configured to store a signal designating (N−R)number of circuit modules to be disconnected from said R number ofinput/output units; and a signal input unit configured to receive asinput a signal designating (N−R) number of circuit modules to bedisconnected from said R number of input/output units, and said controlunit generates the control signal in response to a signal input to saidsignal input unit when a signal having a predetermined initial value isstored in said storage unit and generates said control signal inresponse to a signal stored in said storage unit when a signal having avalue different from said initial value is stored in said storage unit.6. A semiconductor integrated circuit as set forth in claim 1, whereinsaid N number of circuit modules include at least one circuit modulehaving a first function, and at least two circuit modules having asecond function encompassing said first function.
 7. A semiconductorintegrated circuit as set forth in claim 1, wherein the R number ofinput/output units include R number of input/output units from a firstinput/output unit to an R-th input/output unit, the N number of circuitmodules include (R+1) circuit modules from a first circuit module to an(R+1)th circuit module, and the circuit module selection unit isconfigured to select one of an i-th circuit module (i indicates aninteger of 1≦i≦R) or an (i+1)th circuit module in response to thecontrol signal and connect the selected circuit module to the i-thinput/output unit.
 8. A semiconductor integrated circuit as set forth inclaim 7, wherein the R number of input/output units are arranged innumerical order at equal intervals, and the i-th circuit module and the(i+1)th circuit module are arranged at positions so that the distancesfrom the i-th input/output unit become equal.
 9. A semiconductorintegrated circuit as set forth in claim 7, wherein said circuit moduleselection unit has a first switch group including R number of switchcircuits from a first switch circuit to an R-th switch circuit, and asecond switch group including R number of switch circuits from a firstswitch circuit to an R-th switch circuit, an i-th switch circuitbelonging to said first switch group is connected between said i-thinput/output unit and said i-th circuit module, and an i-th switchcircuit belonging to said second switch group is connected between saidi-th input/output unit and said i+1)st circuit module.
 10. Asemiconductor integrated circuit as set forth in claim 9, wherein, whena control signal designating to disconnect an n-th module (n indicatingan integer of 1≦n≦(R+1)) from all of the input/output units is input,when n is an integer of 2 to R, a first switch circuit to (n−1)st switchcircuit belonging to said first switch group turn on and an n-th switchcircuit to R-th switch circuit turn off and a first switch circuit to(n−1)st switch circuit belonging to said second switch group turn offand an n-th switch circuit to R-th switch circuit turn on, when n is theinteger 1, all switch circuits belonging to said first switch group turnoff and all switch circuits belonging to said second switch group turnon, and when n is an integer of (R+1), all switch circuits belonging tosaid first switch group turn on and all switch circuits belonging tosaid second switch group turn off.
 11. A semiconductor integratedcircuit as set forth in claim 10, wherein the circuit comprises acontrol unit for outputting R number of control signals from a firstcontrol signal to an R-th control signal, when disconnecting said n-thcircuit module from all input/output units, said control unit: setting afirst control signal to (n−1)st control signal to a first value andsetting an n-th control signal to an R-th control signal to a secondvalue when n is the integer 2 to R, setting a first control signal toR-th control signal all to said second value when n is the integer 1,and setting a first control signal to R-th control signal all to saidfirst value when n is an integer of (R+1).
 12. A semiconductorintegrated circuit as set forth in claim 11, wherein said control unithas: a plurality of first control lines extending in a first direction,a plurality of second control lines extending in a second directiondifferent from said first direction, intersecting said plurality offirst control lines, and forming R number of intersecting points from afirst intersection to an R-th intersection by said intersections, afirst control unit configured to select one intersecting point inresponse to an input signal from said R number of intersecting points,to activate a first control line and second control line forming saidselected intersecting point or deactivate first control lines and secondcontrol lines forming said R number of intersecting points in responseto said input signal, and a second control unit configured to set afirst control signal to (i−1)st control signal to said first value andset an i-th control signal to R-th control signal to said second valuewhen the first control line and second control line forming said i-thintersecting point are activated and i is an integer of 2 to R andsetting a first control signal to R-th control signal all to said secondvalue when i is the integer 1 and setting first control signal to R-thcontrol signal all to said first value when the first control lines andsecond control lines forming said R number of intersecting points areall deactivated.
 13. A semiconductor integrated circuit as set forth inclaim 1, wherein said circuit module selection unit has at least 2×Rnumber of switch circuits, each of said 2×R number of switch circuits isconnected between one circuit module and one input/output unit, each ofsaid R number of input/output units is connected to a plurality ofcircuit modules through a plurality of switch circuits, each of said Nnumber of circuit modules is connected to one or more input/output unitsthrough one or more switch circuits, one of the plurality of switchcircuits connected to the same input/output unit turns on in response tosaid control signal, and one of the plurality of switch circuitsconnected to the same input/output unit turns on or all turn off inresponse to said control signal.
 14. A semiconductor integrated circuitas set forth in claim 13, wherein said switch circuit has: at least onefirst inverter circuit each having a terminal receiving as input asignal from an input/output unit and a terminal outputting a signal to acircuit module, inverting in logic a signal input to said input terminaland outputting it from said output terminal when set on by said controlsignal, and setting said output terminal to a high impedance state whenset off by said control signal and at least one second inverter circuiteach having a terminal receiving as input a signal from a circuit moduleand a terminal outputting a signal to an input/output unit, inverting inlogic a signal input to said input terminal and outputting it from saidoutput terminal when set on by said control signal, and setting saidoutput terminal to a high impedance state when set off by said controlsignal.
 15. A semiconductor integrated circuit as set forth in claim 14,wherein said first inverter circuit includes a first conductivity typefirst transistor connected in series between a first power line and saidoutput terminal and a second conductivity type third transistorconnected in series between a second power line and said outputterminal, said second inverter circuit includes a first conductivitytype second transistor connected in series between a first power lineand said output terminal and a second conductivity type fourthtransistor connected in series between a second power line and saidoutput terminal, one of said first transistor and said fourth transistoris driven on and the other is driven off in response to a signal inputto said input terminal, and both of said second transistor and saidthird transistor are driven on or are driven off in response to saidcontrol signal.
 16. A semiconductor integrated circuit as set forth inclaim 13, wherein said switch circuit has a first transmission gatecircuit inserted into a path for transmitting a signal from aninput/output unit to a circuit module and turns on or off in response tosaid control signal and a second transmission circuit inserted into apath for transmitting a signal from a circuit module to an input/outputunit and turns on or off in response to said control signal.
 17. Asemiconductor integrated circuit as set forth in claim 13, wherein saidswitch circuit has a fifth transistor inserted into a path fortransmitting a signal from an input/output unit to a circuit module andturns on or off in response to said control signal and a sixthtransistor inserted into a path for transmitting a signal from a circuitmodule to an input/output unit and turns on or off in response to saidcontrol signal.
 18. A semiconductor integrated circuit as set forth inclaim 1, wherein said circuit module selection unit is configured toconnect a signal input terminal of a circuit module disconnected fromall input/output units to interconnect of a predetermined potential inresponse to said control signal.
 19. A semiconductor integrated circuitas set forth in claim 1, wherein combinations of at least two circuitmodules which can be connected to each of the R number of input/outputunits via (through-hole) the circuit module selection unit aredetermined so that a maximum value of delays of all signal pathsconnecting the R number of input/output units and the N number ofcircuit modules via (through-hole) the circuit module selection unitbecomes the smallest.
 20. A semiconductor integrated circuit as setforth in claim 1, wherein combinations of at least two circuit moduleswhich can be connected to each of the R number of input/output units via(through-hole) the circuit module selection unit are determined so thata sum of delays of all signal paths connecting the R number ofinput/output units and the N number of circuit modules via(through-hole) the circuit module selection unit becomes the smallest.21. A semiconductor integrated circuit as set forth in claim 1, whereincombinations of at least two circuit modules which can be connected toeach of the R number of input/output units via (through-hole) thecircuit module selection unit are determined so that a sum of delays ofall of the signal paths becomes the smallest within a range where themaximum value of delays of all signal paths connecting the R number ofinput/output units and the N number of circuit modules via(through-hole) the circuit module selection unit does not exceed apredetermined upper limit value.
 22. A semiconductor integrated circuitas set forth in claim 1, wherein, in the circuit block and the circuitmodule selection unit, the interval of interconnects belonging to thesame interconnect layer is wider in comparison with the N number ofcircuit modules.
 23. A semiconductor integrated circuit as set forth inclaim 1, wherein, in the circuit block and the circuit module selectionunit, the number of vias (through-hole) used for connectinginterconnects belonging to different interconnect layers is larger incomparison with the N number of circuit modules.
 24. A semiconductorintegrated circuit as set forth in claim 1, wherein the N number ofcircuit modules have a higher density of circuit elements per unit areain comparison with the circuit block and the circuit module selectionunit. Due to this, the area of the circuit becomes smaller.
 25. Asemiconductor integrated circuit as set forth in claim 1, wherein thecircuit has N number of power supply switch circuits each of which isinserted in a power supply line of each of the N number of circuitmodules and shutting off the supply of the power to (N−R) number ofcircuit modules not connected to the R number of input/output units in aone-to-one correspondence in response to the control signal.
 26. Asemiconductor integrated circuit as set forth in claim 2, wherein thecircuit has (R+1) number of power switch circuits each of which isinserted in the power supply line of each of the (R+1) number of circuitmodules, said control circuit outputs R number of designation signalsfrom a first designation signal to an R-th designation signal anddesignating by an i-th designation signal whether to disconnect an i-thcircuit module from all of the input/output units, a power switchcircuit inserted into the power supply line of the i-th circuit moduleturns off when said i-th designation signal designates to disconnect thei-th circuit module from all input/output units, and a power switchcircuit inserted into the power supply line of the (R+1)st circuitmodule turns off when an R-th control signal is said first value.
 27. Asemiconductor integrated circuit comprising: a plurality of circuitmodule blocks each including at least three circuit modules; circuitblocks each having a plurality of input/output units for outputting atleast one signal to one circuit module and receiving as input at leastone signal generated in the one circuit module; and a circuit moduleselection unit configured to select R (R indicates an integer of 1≦R<N)number of circuit modules from among N (N indicates an integer of N≧2)number of circuit modules included in each circuit module block inresponse to the input control signal, connect the selected R number ofcircuit modules and R number of input/output units of the circuit blockin a one-to-one correspondence, and connect one circuit module selectedfrom at least two circuit modules in response to the control signal toeach of a plurality of input/output units of the circuit block, wherecircuit modules included in the same circuit module block can replaceeach other's functions.
 28. A semiconductor integrated circuit as setforth in claim 1, wherein the circuit comprises a control unitconfigured to generate the control signal of the circuit moduleselection unit so that any faulty circuit module among the N number ofcircuit modules included in the circuit module block is disconnectedfrom the R number of input/output units.
 29. A semiconductor integratedcircuit as set forth in claim 28, wherein the entire set of circuitmodules included in the plurality of circuit module blocks includes aplurality of partial sets each of which is configured by a plurality ofcircuit modules and has no dealings with the others, when a circuitmodule belonging to a partial set is disconnected from an input/outputunit, the control unit generates the control signal so as to disconnectall other circuit modules belonging to the same partial set as thedisconnected circuit module from the input/output unit.
 30. Asemiconductor integrated circuit as set forth in claim 29, wherein thecircuit has a plurality of power supply switch circuits each of which isinserted in the power supply line of each of the plurality of partialsets and shut off the supply of the power to the partial setdisconnected from the input/output units.
 31. A semiconductor integratedcircuit as set forth in claim 27, wherein the circuit has a circuitmodule commonly used by a plurality of circuit module blocks and havinga function of encompassing all or part of the functions of the othercircuit modules included in the plurality of circuit module blocks. 32.A method of producing of a semiconductor integrated circuit, comprising:a first step of forming, on a semiconductor substrate, a circuit havingN (N indicates an integer of N≧2) number of circuit modules which canreplace each other's functions, circuit blocks each having R (Rindicates an integer of 1≦R<N) input/output units for outputting atleast one signal to one circuit module and receiving as input at leastone signal generated in the one circuit module, a circuit moduleselection unit configured to select R number of circuit modules fromamong the N number of circuit modules in response to the input controlsignal and connect the selected R number of circuit modules and R numberof input/output units of the circuit block in a one-to-onecorrespondence, a storage unit configured to store a signal having apredetermined initial value, a signal input unit configured to receiveas input a signal designating (N−R) number of circuit modules whichshould be disconnected from the R number of input/output units, and acontrol unit configured to generate the control signal in accordancewith a signal input to the signal input unit when the signal having theinitial value is stored in the storage unit and generate the controlsignal in accordance with the signal stored in the storage unit when asignal having a value different from the initial value is stored in thestorage unit; a second step of inputting a signal designating (N−R)number of circuit modules to the signal input unit and inspecting the Rnumber of circuit modules connected to the R number of input/outputunits in accordance with the input signal; a third step of inputting asignal designating a new (N−R) number of circuit modules including afaulty circuit module to the signal input unit and again performs theinspection of the second step when a faulty circuit module is detectedin the inspection of the second step; and a fourth step of determining asignal designating the (N−R) number of circuit modules which should bedisconnected from the R number of input/output units, and writing itinto the storage unit in accordance with a signal input to the signalinput unit when a faulty circuit module is not detected in theinspection of the second step.